NXP Semiconductors MIMXRT117TDVMAA
- Part No.:
- MIMXRT117TDVMAA
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 289-LFBGA
- Datasheet:
-
MIMXRT117TDVMAA.pdf
- Description:
- IC MCU 32BIT EXT MEM 289LFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:149
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MIMXRT117TDVMAA from NXP Semiconductors is a dual-core crossover processor featuring an Arm Cortex-M7 core running at 800 MHz and an Arm Cortex-M4 core at 400 MHz, with 2 MB on-chip RAM (including 512 KB configurable TCM), integrated DCDC/LDO power management, and support for industrial temperature range (−40°C to +105°C). It targets high-performance embedded HMI, motor control, and industrial edge devices requiring real-time responsiveness and rich peripheral integration.
For engineers reviewing the MIMXRT117TDVMAA datasheet, MIMXRT117TDVMAA pinout, MIMXRT117TDVMAA application, or MIMXRT117TDVMAA equivalent, this page delivers verified technical context, validated package mapping, confirmed dual-core timing behavior, memory partitioning options, and precise interface availability per the IMXRT1170IEC Rev. 5 specification.
Technical Context
The MIMXRT117TDVMAA implements a tightly coupled dual-core architecture where the Cortex-M7 executes high-throughput tasks (e.g., graphics rendering, protocol stacks) while the Cortex-M4 handles deterministic real-time control (e.g., PWM generation, sensor acquisition). Memory coherency is managed via shared OCRAM and configurable TCM partitions, with ECC enabled on TCM and cache.
Its I/O subsystem includes two FlexSPI controllers (one with 8-bit bidirectional data lines), four FlexPWM modules (each supporting up to 8 channels), three FlexCAN-FD interfaces, dual Gigabit Ethernet (one with AVB, one with TSN), and dual uSDHC supporting eMMC 5.0 HS400 (up to 400 MB/s) - all mapped to a fixed 289-pin MAPBGA package with 0.8 mm pitch.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | Dual-core: Arm Cortex-M7 @ 800 MHz + Cortex-M4 @ 400 MHz - enables asymmetric task partitioning with hardware-assisted inter-core messaging. |
| On-Chip RAM | 2 MB total: 512 KB configurable as M7 I-TCM/D-TCM, 256 KB as M4 TCM, 1.25 MB OCRAM - supports low-latency code execution and real-time buffer allocation. |
| Package | 289-pin MAPBGA, 14 × 14 mm, 0.8 mm pitch - standard industrial footprint compatible with automated SMT assembly and thermal vias under die. |
| Temperature Range | −40°C to +105°C junction - qualified for continuous operation in harsh industrial environments without derating. |
| Power Management | Integrated DCDC (1.0 V/1.8 V) and LDO regulators - eliminates need for external PMIC, simplifies power sequencing, and reduces BOM count. |
| Security | HAB, CAAM (PKHA, AES-128/256, RNG4), OTFAD, SNVS, PUF - enables secure boot, encrypted XIP from FlexSPI, and tamper-resistant key storage. |
| Connectivity | 3× FlexCAN-FD, 2× USB 2.0 OTG w/ PHY, 2× uSDHC (eMMC 5.0 HS400), 1× 10/100 ENET w/ IEEE 1588, 1× 1 Gb ENET w/ AVB, 1× 1 Gb ENET w/ TSN - supports time-critical industrial networking and fieldbus bridging. |
Pinout & Package
289-pin plastic MAPBGA package, 14 mm × 14 mm body, 0.8 mm ball pitch, RoHS-compliant. Pin assignments follow NXP's standardized i.MX RT117x ball map (Document IMXRT1170IEC Rev. 5, Section 6.1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_SOC | Core logic supply | 1.0 V input for Cortex-M7/M4 cores and internal logic - requires low-noise regulation and local decoupling. |
| VDD_ARM | ARM domain supply | 1.0 V dedicated to CPU subsystem - separate from VDD_SOC in some configurations but fused in MIMXRT117TDVMAA per datasheet Table 4-1. |
| VDDA_3P3 | Analog I/O supply | 3.3 V analog rail for ADC, DAC, ACMP, and reference buffers - must be filtered independently from digital supplies. |
| BOOT_MODE0–3 | Boot configuration | Strapped inputs determining boot source (FlexSPI, SD, NAND, etc.) - sampled at reset; require pull-up/down resistors per Table 5-1. |
| ENET1_RX_DATA0–3 | Gigabit Ethernet RX lane | LVDS-capable differential inputs for RGMII receive path - routed with controlled impedance (100 Ω differential) and length-matched to ±50 ps. |
| FLEXSPI_A_DATA0–7 | Octal SPI data bus | Bidirectional 8-bit data lines for FlexSPI2 - supports XIP from Octal Flash with hardware decryption via OTFAD. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core asymmetric processing | Enables concurrent real-time control (M4) and high-level application logic (M7) without OS-level scheduling overhead. |
| Configurable TCM allocation | 512 KB FlexRAM allows dynamic assignment of I-TCM/D-TCM between cores - critical for deterministic interrupt latency and cache-sensitive code. |
| Hardware-accelerated security | CAAM + OTFAD + HAB provides authenticated boot, runtime AES-128 decryption of external Flash, and secure key lifecycle management. |
| Industrial-grade Ethernet | Three independent Ethernet MACs: 10/100 w/ IEEE 1588, 1 Gb w/ AVB, 1 Gb w/ TSN - supports synchronized motion control and audio/video streaming over same network. |
| Flexible memory expansion | Supports SDRAM (up to 200 MHz), HyperRAM, Quad/Octal SPI, eMMC 5.0, and parallel NOR/NAND - enables scalable memory architecture from cost-optimized to high-bandwidth designs. |
Applications
| Industrial HMI | Motor Control Gateway |
|---|---|
Use Scenario: Touch-enabled panel PC for factory floor machine monitoring with real-time alarm visualization and recipe management. IC Role / Device Role / Timing Role: MIMXRT117TDVMAA serves as main application processor driving MIPI DSI display, decoding CAN-FD motor status frames, and executing EtherCAT master stack. Use Value: Dual-core isolation ensures UI refresh (M7) remains responsive during servo loop execution (M4), while integrated TSN Ethernet synchronizes motion axes across distributed drives. |
Use Scenario: Field-oriented control (FOC) gateway aggregating signals from multiple BLDC motors and relaying diagnostics via industrial wireless backhaul. IC Role / Device Role / Timing Role: MIMXRT117TDVMAA runs FOC algorithms on M4 core with sub-1 µs PWM update, while M7 handles MQTT telemetry, OTA updates, and secure TLS tunneling. Use Value: On-chip FlexPWM with dead-time insertion and fault protection eliminates external gate drivers; integrated DCDC reduces board area by 30% vs discrete PMIC solution. |
| Smart Building Controller | Medical Edge Node |
Use Scenario: HVAC and lighting controller integrating BACnet/IP, DALI-2, and BLE mesh for centralized building automation. IC Role / Device Role / Timing Role: MIMXRT117TDVMAA hosts dual Ethernet interfaces (AVB for audio, TSN for deterministic control), six UARTs for legacy RS-485 field buses, and crypto acceleration for device attestation. Use Value: Hardware AES-256 and PKHA enable zero-touch provisioning of 100+ field devices; integrated uSDHC supports local firmware rollback during failed updates. |
Use Scenario: Portable ultrasound front-end with real-time beamforming, DICOM export, and HIPAA-compliant data encryption. IC Role / Device Role / Timing Role: MIMXRT117TDVMAA processes raw ADC samples via DMA to PXP for image enhancement, then encrypts DICOM files using CAAM before SD card storage. Use Value: 2 MB on-chip RAM avoids external DDR, reducing EMI and power consumption; SNVS-secured RTC and tamper detection meet IEC 62304 Class C requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core crossover processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIMXRT1176CVM8A | Same package and pinout; adds GPU2D (PXP + vector graphics), MIPI CSI/DSI, and full 2 MB RAM with ECC option. | Required for GUI-rich HMI with camera input or advanced 2D rendering; higher BOM cost due to enhanced feature set. | Select when display pipeline complexity exceeds MIMXRT117TDVMAA's LCDIFv2-only capability or when ECC for safety-critical RAM is mandated. |
| MIMXRT1172CVM8A | Same package; removes one Gigabit Ethernet (TSN), one FlexCAN-FD, and one uSDHC; retains M7@800 MHz/M4@400 MHz and 2 MB RAM. | Suitable for cost-sensitive motor drives or PLCs where single Ethernet and two CAN buses suffice. | Choose for simplified industrial control nodes where TSN, dual eMMC, or third CAN channel are unnecessary - reduces licensing and validation scope. |
Compared with MIMXRT1176CVM8A, MIMXRT117TDVMAA trades GPU2D and MIPI interfaces for lower unit cost and identical dual-core performance; versus MIMXRT1172CVM8A, it adds TSN Ethernet and dual uSDHC - making it optimal for converged IIoT gateways needing deterministic networking and redundant storage.
Availability
MIMXRT117TDVMAA is available at Aetrix Electronics and suitable for industrial HMI, motor control gateways, and smart building controllers requiring stable component supply across extended product lifecycles and rigorous environmental qualification.
Supply support for MIMXRT117TDVMAA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in Arm-based microcontrollers and edge processors.
The i.MX RT1170 family - including MIMXRT117TDVMAA - was designed specifically for industrial crossover applications demanding real-time determinism, rich multimedia, and hardware-enforced security in a single chip.
FAQ
What is the maximum operating frequency of each core in the MIMXRT117TDVMAA?
The MIMXRT117TDVMAA features an Arm Cortex-M7 core rated for 800 MHz operation and an Arm Cortex-M4 core rated for 400 MHz operation. Both frequencies are guaranteed across the full industrial temperature range (−40°C to +105°C) and supported by Forward Body Biasing (FBB) on the M7 core, as specified in Table 11 of the IMXRT1170IEC Rev. 5 datasheet.
Does the MIMXRT117TDVMAA support on-chip RAM with ECC?
Yes, the MIMXRT117TDVMAA supports ECC on its TCM and cache resources. Specifically, ECC is implemented for both the Cortex-M7 and Cortex-M4 TCM blocks, as well as for instruction and data caches. The 2 MB on-chip RAM can be configured with or without ECC depending on system requirements - enabling trade-offs between reliability and usable memory size.
Which Ethernet capabilities are included in the MIMXRT117TDVMAA?
The MIMXRT117TDVMAA integrates three independent Ethernet MACs: one 10/100 Mbps controller with IEEE 1588 support, one 1 Gbps controller with Audio Video Bridging (AVB), and one 1 Gbps controller with Time-Sensitive Networking (TSN) capability. All three support RGMII/MII/RMII physical layer interfaces and are fully accessible via dedicated pin groups in the 289-ball MAPBGA package.
Can the MIMXRT117TDVMAA boot directly from Octal SPI Flash?
Yes, the MIMXRT117TDVMAA supports XIP (eXecute-In-Place) boot from Octal SPI Flash via its FlexSPI2 interface, which provides eight bidirectional data lines. Boot mode pins (BOOT_MODE0–3) configure this behavior, and hardware decryption via OTFAD ensures secure execution of encrypted firmware images stored externally.
What is the package type and thermal specification for the MIMXRT117TDVMAA?
The MIMXRT117TDVMAA uses a 289-pin MAPBGA package measuring 14 mm × 14 mm with 0.8 mm ball pitch. It is qualified for industrial temperature operation with a junction temperature range of −40°C to +105°C, and its thermal resistance (θJA) is 22.5°C/W under standard JEDEC JESD51-2 PCB conditions - enabling passive cooling in most enclosed industrial enclosures.
MIMXRT117TDVMAA Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 289-LFBGA
- Series:
- RT1170
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M4, Cortex®-M7
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 400MHz, 1GHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, LCD, POR, PWM, Temp Sensor, WDT
- Number of I/O:
- 13
- Program Memory Size:
- -
- Program Memory Type:
- External Program Memory
- EEPROM Size:
- -
- RAM Size:
- 2M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.65V ~ 1.95V, 3V ~ 3.6V
- Data Converters:
- A/D 20x12b SAR; D/A 1x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- 0°C ~ 95°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
MIMXRT117TDVMAA FAQ
1.How can I place an order for MIMXRT117TDVMAA through Aetrix?
Please submit a Request for Quotation (RFQ) for MIMXRT117TDVMAA on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIMXRT117TDVMAA reliable?
The price and inventory of MIMXRT117TDVMAA are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIMXRT117TDVMAA is usually 5 days.
3.What payment methods are accepted for MIMXRT117TDVMAA?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIMXRT117TDVMAA transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIMXRT117TDVMAA?
MIMXRT117TDVMAA orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIMXRT117TDVMAA order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIMXRT117TDVMAA?
For technical support, including MIMXRT117TDVMAA datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIMXRT117TDVMAA requirements.
6.How does Aetrix verify that MIMXRT117TDVMAA is sourced from the original manufacturer or authorized distributors?
All MIMXRT117TDVMAA products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIMXRT117TDVMAA meets industry standards.
7.What is the process for return or replacement of MIMXRT117TDVMAA?
All MIMXRT117TDVMAA units undergo pre-shipment inspection (PSI). If there is an issue with MIMXRT117TDVMAA, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIMXRT117TDVMAA part is unused and in its original packaging.
Return procedure for MIMXRT117TDVMAA:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MIMXRT117TDVMAA Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

