NXP Semiconductors MIMXRT595SFFOCR

Overview

MIMXRT595SFFOCR from NXP Semiconductors is a dual-core low-power crossover processor integrating an Arm Cortex-M33 CPU (up to 275 MHz) and a Cadence Tensilica Fusion F1 DSP (up to 275 MHz), with 5 MB shared SRAM, on-the-fly AES decryption for FlexSPI, and hardware TrustZone security. It targets voice-enabled edge devices requiring concurrent real-time control and audio processing.

For engineers reviewing the MIMXRT595SFFOCR datasheet, MIMXRT595SFFOCR pinout, MIMXRT595SFFOCR application, or MIMXRT595SFFOCR equivalent, key selection factors include dual-core asymmetric processing capability, integrated PUF-based secure key generation, MIPI DSI support for embedded displays, and FOWLP249 package compatibility with high-density PCB layouts.

Technical Context

The MIMXRT595SFFOCR implements a tightly coupled dual-domain architecture: the Cortex-M33 handles real-time system control, secure boot, and peripheral management, while the Fusion F1 DSP executes computationally intensive audio preprocessing-including DMIC decimation, voice activation detection, and acoustic echo cancellation-using dedicated 8 KB SRAM banks. Both cores share access to 5 MB low-leakage SRAM and operate from independent power domains.

Its clocking system includes a main PLL supporting up to 275 MHz for both CPUs, a dedicated audio PLL, and dual trimmable FRO oscillators (192/96 MHz at ±1% accuracy, tunable to ±0.1%). Power management enables independent domain shutdown (e.g., DSP off in Deep_sleep), per-SRAM partition retention, and five VDDIO rails for mixed-voltage I/O interfacing.

Key Specifications

Pinout & Package

FOWLP249 (Fan-out Wafer-Level Package): 7.0 mm × 7.0 mm × 0.725 mm body, 0.4 mm ball pitch, 249 I/O balls. Designed for high-density PCBs with improved thermal and electrical performance over QFN/LGA alternatives.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core audio-control processor applications.

Compared with MIMXRT595SFFOC, MIMXRT595SFFOCR provides identical performance and features in tape-and-reel format for high-throughput manufacturing, while MIMXRT595SVFFOC adds validated voice software - enabling faster time-to-market for speech-centric products without compromising hardware security or processing capability.

Availability

MIMXRT595SFFOCR is available at Aetrix Electronics and suitable for voice-controlled smart speakers, industrial HMIs, portable medical assistants, and automotive cabin interfaces requiring stable component supply across multi-year production cycles.

Supply support for MIMXRT595SFFOCR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in ARM-based microcontrollers and edge AI processing.

The i.MX RT500 series was designed to bridge the gap between microcontrollers and application processors - delivering MCU-level power efficiency with application-processor-class audio and graphics capabilities for intelligent edge devices.

FAQ

What is the maximum operating frequency of the Cortex-M33 core in the MIMXRT595SFFOCR?

The Cortex-M33 core in the MIMXRT595SFFOCR operates at up to 275 MHz under recommended conditions. This maximum frequency is supported across the full industrial temperature range (–20 °C to +85 °C) when VDDCORE is supplied within 0.7 V to 1.155 V and thermal limits are maintained. The MIMXRT595SFFOCR datasheet specifies this value in Table 8 under "CPU (Cortex-M33) clock frequency" with no derating required for standard operation.

Does the MIMXRT595SFFOCR support execute-in-place (XiP) from external flash memory?

Yes, the MIMXRT595SFFOCR supports execute-in-place from external Octal/Quad SPI flash via its two FlexSPI interfaces, with one interface featuring on-the-fly AES decryption (OTFAD). This enables secure XiP boot and runtime execution without loading code into internal SRAM - a key capability confirmed in Section 1 and Table 1 of the IMXRT500EC datasheet for all MIMXRT595 variants including MIMXRT595SFFOCR.

What package type and dimensions does the MIMXRT595SFFOCR use?

The MIMXRT595SFFOCR uses the FOWLP249 package: a 249-ball fan-out wafer-level package measuring 7.0 mm × 7.0 mm × 0.725 mm with 0.4 mm ball pitch. This is explicitly stated in Table 1 of the IMXRT500EC datasheet and confirmed in Figure 4's part number diagram where "FO" denotes FOWLP and "249" indicates ball count. Thermal resistance (RθJA = 29.6 °C/W) is characterized per JEDEC JESD51-2A.

How many digital microphone (DMIC) channels does the MIMXRT595SFFOCR support?

The MIMXRT595SFFOCR supports up to 8 digital microphone channels with integrated decimation filters and voice activation detection hardware. This capability is documented in Section 1 ("Digital peripherals"), Section 1.5 ("Communication interface"), and the block diagram (Figure 1) of the IMXRT500EC datasheet - and applies to all MIMXRT595 variants, including MIMXRT595SFFOCR, as confirmed in Table 1 where "DSP" is marked "Yes".

Is the MIMXRT595SFFOCR pin-compatible with other i.MX RT500 family members in the FOWLP249 package?

Yes, the MIMXRT595SFFOCR is pin-compatible with other i.MX RT500 devices in the FOWLP249 package (e.g., MIMXRT555SFFOC, MIMXRT533SFFOC), sharing identical ball map, power rail assignments, and I/O functionality per pin. This is verified in the i.MX RT500 Reference Manual and confirmed by NXP's package compatibility guidance - enabling hardware reuse across performance tiers while maintaining identical PCB layout and thermal design.