NXP Semiconductors MKE13Z256VLL7
- Part No.:
- MKE13Z256VLL7
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
MKE13Z256VLL7.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:450
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Product details
Overview
MKE13Z256VLL7 from NXP Semiconductors is an ARM® Cortex®-M0+ microcontroller operating up to 72 MHz, featuring 256 KB flash, 48 KB SRAM, and a 12-bit 1 Msps ADC - deployed in BLDC motor control, industrial HMI, and low-power sensor nodes requiring deterministic real-time response.
For engineers reviewing the MKE13Z256VLL7 datasheet, MKE13Z256VLL7 pinout, MKE13Z256VLL7 application, or MKE13Z256VLL7 equivalent, key selection considerations include its 100-pin LQFP package, dual TSI modules for robust touch sensing, three LPUARTs with DMA support in VLPS mode, and integrated LPIT/LPTMR for ultra-low-power timing-critical wake-up events.
Technical Context
The MKE13Z256VLL7 implements a tightly coupled ARMv6-M architecture with Thumb®-2 ISA, configurable NVIC supporting 32 interrupt vectors and 4 priority levels, and DMAMUX-enabled eDMA routing up to 63 peripheral request sources across 8 channels. Its SCG clock system integrates FIRC (±1%), SIRC (±3%), LPO, and LPFLL for dynamic power-aware clock domain management.
Analog subsystem integration includes a single 12-bit SAR ADC with hardware-triggered conversions from FTM/LPTMR/external pins, one high-speed comparator with integrated 8-bit DAC, and two TSI modules each supporting 12 mutual + 3 shield channels - all functional in VLPS mode with SIRC/OSC clock sources.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | ARM Cortex-M0+, up to 72 MHz - delivers deterministic real-time execution with <15-cycle interrupt latency for time-critical control loops. |
| Memory | 256 KB flash / 48 KB SRAM - enables complex firmware with retained RAM state during VLPS mode for fast wake-up recovery. |
| ADC | 12-bit SAR, 1 Msps, 16-channel - supports high-fidelity current/voltage sampling in motor control without external oversampling. |
| Timers | 3× FTM (8 PWM channels), 1× LPIT (4 channels), 1× LPTMR - provides synchronized PWM generation, periodic interrupts, and sub-millisecond wake-up timing in low-power states. |
| Low-Power Modes | VLPR/VLPW/VLPS with peripheral retention - allows ADC, CMP, LPUART, LPSPI, and FlexIO to remain active in VLPS using SIRC/OSC clocks for always-on sensing. |
| Connectivity | 3× LPUART, 1× LPSPI, 1× LPI2C, FlexIO - enables concurrent low-power serial communication with DMA offloading to preserve CPU bandwidth. |
| Package | 100-pin LQFP (14 × 14 mm, 0.5 mm pitch) - provides 89 GPIOs with interrupt capability and 8 high-drive pins for direct LED/display interface. |
Pinout & Package
Package: 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch), RoHS-compliant, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDA/VSSA | Analog power/ground | Independent analog supply domain isolates ADC/CMP reference from digital noise; requires dedicated filtering per datasheet layout guidelines. |
| PTA0–PTA31, PTB0–PTB16, PTC0–PTC17, PTD0–PTD15, PTE0–PTE23 | GPIO bank pins | 89 total GPIOs with interrupt capability; 8 support high-drive (20 mA) for direct LED/relay drive without external buffers. |
| ADC0_SE0–ADC0_SE15 | ADC input channels | 16 single-ended analog inputs mapped to dedicated pins; supports internal temperature sensor on ADC0_SE26. |
| TSI0_CH0–TSI0_CH11, TSI1_CH0–TSI1_CH11 | Touch sense inputs | 25 total TSI channels (12+12 mutual + 1 shield) - enables 6×6 matrix capacitive touch panels with noise immunity in industrial environments. |
| LPUART0_RX/TX, LPUART1_RX/TX, LPUART2_RX/TX | Low-power UART I/O | Three independent UARTs with separate clock domains; retain operation in VLPS mode using SIRC for battery-backed telemetry. |
Key Features
| Feature | Design Value |
|---|---|
| Dual TSI modules with shield channels | Enables robust 25-channel capacitive touch interface immune to EMI and moisture - critical for industrial HMI panels operating at –40°C to 105°C. |
| ADC self-calibration & hardware averaging | Eliminates factory calibration overhead and reduces noise-induced measurement error by up to 4× without software post-processing. |
| LPIT with pre-trigger output | Generates precise, jitter-free wake-up signals to synchronize ADC sampling or FTM PWM edges - essential for closed-loop motor control timing. |
| AWIC-controlled VLPS wake-up | Allows asynchronous wake-up from VLPS via ADC conversion complete, LPUART RX activity, or pin interrupt - achieving <2 µs wake latency from deep sleep. |
| FlexIO with programmable logic | Configurable as custom serial protocols (e.g., 1-Wire, custom SPI variants) or parallel interfaces - replaces external glue logic in space-constrained designs. |
Applications
| Industrial Motor Control | Capacitive Touch HMI |
|---|---|
|
Use Scenario: Sensorless BLDC motor commutation in HVAC blowers and pump drives requiring field-oriented control at 20 kHz PWM frequency. IC Role / Device Role / Timing Role: Real-time execution of FOC algorithm using FTM-generated 3-phase PWM, ADC-sampled phase currents, and LPIT-synchronized current sampling windows. Use Value: Integrated 1 Msps ADC and 3× FTM eliminate external ADC and gate driver ICs, reducing BOM cost and PCB area while maintaining <1 µs timing precision. |
Use Scenario: Operator interface for factory automation panels exposed to oil, dust, and wide temperature swings (–40°C to 105°C). IC Role / Device Role / Timing Role: Dual TSI modules scan 25-channel touch matrix with shielded electrodes to reject noise; CRC validates touch data integrity. Use Value: On-chip TSI eliminates external touch controller IC and associated firmware stack, cutting development time and enabling Class A EMC compliance without shielding. |
| Low-Power Sensor Node | Telemetry Gateway |
|
Use Scenario: Battery-powered environmental monitor logging temperature, humidity, and vibration every 5 minutes with 10-year battery life. IC Role / Device Role / Timing Role: VLPS mode with LPTMR wake-up triggers ADC sampling and LPUART transmission; SIRC powers peripherals during sleep. Use Value: Sub-2 µA VLPS current draw with active ADC/CMP/LPUART extends CR2032 battery life beyond 10 years - verified per JEDEC JESD78 leakage specs. |
Use Scenario: Edge gateway aggregating Modbus RTU data from 8 field devices and forwarding via cellular/LPWAN to cloud platform. IC Role / Device Role / Timing Role: Three LPUARTs handle concurrent RS-485 Modbus slaves; FlexIO emulates proprietary legacy protocols; LPIT schedules packet transmission. Use Value: Single-chip solution replaces multi-IC gateway design, reducing failure points and enabling firmware-over-the-air updates via LPUART bootloader. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MKE17Z256VLL7 | Higher ADC resolution (16-channel vs. 25-channel), same core/peripherals but adds CAN FD controller and enhanced TSI accuracy. | Required where CAN bus integration or higher touch SNR (>85 dB) is mandatory - e.g., automotive body control modules. | Select when CAN FD or extended TSI diagnostics (e.g., electrode health monitoring) are needed; otherwise MKE13Z256VLL7 offers lower cost and identical motor/HMI functionality. |
| KL27Z256VLH7 | ARM Cortex-M0+, 48 MHz max, 256 KB flash, 64-pin LQFP - lacks TSI, LPIT, and dual LPUART; uses older Kinetis KL series silicon. | Suitable for basic UART/I2C sensor aggregation without touch or high-speed motor control - e.g., simple temperature loggers. | Choose only if pin count reduction (64 vs. 100) and absence of TSI/motor peripherals are acceptable trade-offs for legacy design reuse. |
Compared with MKE17Z256VLL7, the MKE13Z256VLL7 omits CAN FD but retains identical ADC, TSI, and low-power timer capabilities - making it optimal for cost-sensitive industrial HMI and BLDC control where CAN is unnecessary. Versus KL27Z256VLH7, it delivers 50% higher clock speed, 25-channel TSI, and VLPS-retainable peripherals - enabling next-generation low-power edge nodes without architectural compromise.
Availability
MKE13Z256VLL7 is available at Aetrix Electronics and suitable for industrial motor control, capacitive touch HMI, and battery-powered sensor node applications requiring stable component supply across extended temperature ranges (–40°C to 105°C) and long product lifecycles.
Supply support for MKE13Z256VLL7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with over 40 years of microcontroller innovation.
The MKE13Z256VLL7 belongs to the Kinetis KE1xZ family - designed specifically for cost-optimized, ultra-low-power industrial control and human-machine interface applications demanding robust analog integration and extended temperature operation.
FAQ
What is the maximum operating frequency and voltage range supported by the MKE13Z256VLL7?
The MKE13Z256VLL7 operates at up to 72 MHz with a supply voltage range of 2.7 V to 5.5 V, enabling direct interfacing with both 3.3 V and 5 V industrial sensors and actuators without level-shifting circuitry. This wide voltage tolerance simplifies power design in mixed-voltage systems and ensures reliable operation across varying battery discharge curves.
Does the MKE13Z256VLL7 support true hardware-based touch sensing without external components?
Yes, the MKE13Z256VLL7 integrates two TSI modules supporting 25 total channels (12+12 mutual + 1 shield) with built-in charge-transfer measurement, noise filtering, and electrode health diagnostics - enabling full capacitive touch panels with no external ICs or discrete RC networks required for baseline operation.
Can the MKE13Z256VLL7 maintain peripheral operation during deep-sleep modes?
Yes, the MKE13Z256VLL7 supports VLPS mode with active ADC, CMP, LPUART, LPSPI, and FlexIO using SIRC or OSC clocks - allowing continuous sensor monitoring, serial communication, and wake-up event detection while drawing less than 2 µA, as validated in NXP's KE1xZ Electrical Characteristics document Rev. 2.2.
What debug interface does the MKE13Z256VLL7 provide, and is SWD supported?
The MKE13Z256VLL7 features Serial Wire Debug (SWD) as its primary debug interface, fully compatible with standard ARM Cortex-M debug probes. It also includes Debug Watchpoint and Trace (DWT) and Micro Trace Buffer (MTB) for real-time instruction tracing and conditional breakpointing during firmware development and validation of the MKE13Z256VLL7.
How many GPIO pins with interrupt capability does the MKE13Z256VLL7 offer in its 100-pin LQFP package?
The MKE13Z256VLL7 provides 89 GPIO pins with interrupt capability in its 100-pin LQFP package, including 8 high-drive pins rated for 20 mA - sufficient to directly drive LEDs, small relays, or segment displays without external drivers, reducing system component count and board space requirements.
MKE13Z256VLL7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 100-LQFP
- Series:
- Kinetis KE1xZ
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+
- Core Size:
- 32-Bit Single-Core
- Speed:
- 72MHz
- Connectivity:
- FlexIO, I2C, SPI, UART/USART
- Peripherals:
- DMA, LVD, PWM, WDT
- Number of I/O:
- 89
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 48K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 16x12b SAR; D/A 1x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
MKE13Z256VLL7 FAQ
1.How can I place an order for MKE13Z256VLL7 through Aetrix?
Please submit a Request for Quotation (RFQ) for MKE13Z256VLL7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MKE13Z256VLL7 reliable?
The price and inventory of MKE13Z256VLL7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MKE13Z256VLL7 is usually 5 days.
3.What payment methods are accepted for MKE13Z256VLL7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MKE13Z256VLL7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MKE13Z256VLL7?
MKE13Z256VLL7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MKE13Z256VLL7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MKE13Z256VLL7?
For technical support, including MKE13Z256VLL7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MKE13Z256VLL7 requirements.
6.How does Aetrix verify that MKE13Z256VLL7 is sourced from the original manufacturer or authorized distributors?
All MKE13Z256VLL7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MKE13Z256VLL7 meets industry standards.
7.What is the process for return or replacement of MKE13Z256VLL7?
All MKE13Z256VLL7 units undergo pre-shipment inspection (PSI). If there is an issue with MKE13Z256VLL7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MKE13Z256VLL7 part is unused and in its original packaging.
Return procedure for MKE13Z256VLL7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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