NXP Semiconductors MKE17Z256VLH7
- Part No.:
- MKE17Z256VLH7
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
MKE17Z256VLH7.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 64LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:785
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MKE17Z256VLH7 from NXP Semiconductors is a 64-pin LQFP ARM® Cortex®-M0+ microcontroller operating up to 72 MHz, featuring 256 KB flash, 48 KB SRAM, and integrated 12-bit 1 Msps ADC - deployed in BLDC motor control, industrial HMI, and low-power sensor nodes.
For engineers reviewing the MKE17Z256VLH7 datasheet, MKE17Z256VLH7 pinout, MKE17Z256VLH7 application, or MKE17Z256VLH7 equivalent, key selection criteria include its 58 GPIOs with high-drive capability, dual TSI modules for robust touch sensing, and full low-power peripheral operation (LPUART/LPSPI/LPI2C/ADC/CMP) in VLPS mode.
Technical Context
The MKE17Z256VLH7 implements an ARMv6-M architecture with Thumb®-2 ISA, configurable NVIC supporting 32 interrupt vectors and 4 priority levels, and a crossbar switch enabling concurrent bus master access. Its SCG clock system integrates FIRC (48 MHz ±1%), SIRC (8/2 MHz ±3%), LPO (128 kHz), LPFLL, and external crystal support (4–40 MHz).
Power management is handled by PMC with six operational modes (Run, Wait, Stop, VLPR, VLPW, VLPS); peripherals like ADC, CMP, LPTMR, LPIT, FlexIO, and all three LPUARTs remain functional in VLPS mode using SIRC or OSC clocks. The device includes eDMA (8 channels, extended to 63 via DMAMUX) and hardware CRC-16/32 for data integrity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | ARM Cortex-M0+, 72 MHz max - delivers deterministic real-time control with minimal power overhead. |
| Memory | 256 KB flash / 48 KB SRAM - sufficient for complex motor control algorithms and firmware updates in-field. |
| ADC | 12-bit SAR, 1 Msps, 16-channel - enables high-resolution current/voltage sampling in BLDC commutation loops. |
| Timers | 3× FTM (8 PWM channels total), 1× LPIT (4 channels), 1× LPTMR - supports precise timing-critical tasks across power modes. |
| Connectivity | 3× LPUART, 1× LPSPI, 1× LPI2C, FlexIO - provides flexible, low-power serial communication for sensor fusion and host interfaces. |
| Touch Sensing | 2× TSI modules, 47 total touch channels - delivers noise-immune capacitive touch for industrial panel interfaces. |
| Supply Range | 2.7–5.5 V - compatible with wide-input industrial power rails and battery-backed systems. |
| Temp Range | –40 to 105 °C - qualified for under-hood automotive and factory-floor embedded applications. |
Pinout & Package
64-pin LQFP (VLH7), 10 mm × 10 mm × 1.4 mm, 0.5 mm pitch. Package conforms to JEDEC MO-153AC standard (drawing 98ASS23234W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Power supply and ground | Dedicated analog/digital power pins enable clean separation for mixed-signal stability. |
| PTA0–PTA31, PTB0–PTB31, etc. | GPIO multiplexed I/O | 58 total GPIOs with interrupt, high-drive (20 mA), and configurable pull-up/down - supports direct LED driving and sensor interfacing. |
| ADC0_SE0–ADC0_SE15 | Analog input channels | 16 single-ended inputs mapped to dedicated pins - allows simultaneous sampling of motor phase currents and DC bus voltage. |
| TSI0_CH0–TSI0_CH12, TSI1_CH0–TSI1_CH12 | Touch sense inputs | 47 total TSI channels distributed across two modules - enables multi-zone touch panels without external controllers. |
| LPUART0_RX/TX, LPUART1_RX/TX, LPUART2_RX/TX | Low-power UART I/O | Three independent UARTs with DMA and VLPS wake capability - ideal for fault-reporting telemetry in sleep-mode systems. |
| FTM0_CH0–FTM0_CH7, FTM1_CH0–FTM1_CH7, FTM2_CH0–FTM2_CH7 | PWM output channels | 24 total FTM channels (8 per module) with deadtime insertion - supports 3-phase BLDC gate drive with hardware safety features. |
Key Features
| Feature | Design Value |
|---|---|
| VLPS-mode peripheral retention | ADC, CMP, LPUART×3, LPSPI, LPI2C, LPIT, LPTMR, FlexIO, and DMA remain active - enables responsive wake-on-event without full MCU restart. |
| Integrated temperature sensor | On-die sensor connected to ADC channel AD26 - supports real-time thermal monitoring of motor windings or PCB hotspots. |
| Self-calibrating ADC | Hardware-initiated calibration routine corrects gain/offset drift - maintains measurement accuracy over temperature and time without host intervention. |
| Asynchronous Wake-up Controller (AWIC) | Dedicated logic for Stop/VLPS wake events - reduces wake latency to <5 µs for critical interrupts like overcurrent or emergency stop. |
| FlexIO programmable interface | Configurable logic blocks emulate SPI/I2C/UART/RGB/IR protocols - eliminates need for external protocol translators in space-constrained designs. |
| Secure debug disable | Flash configuration field (0x40E) locks SWD memory access - prevents firmware extraction while allowing mass erase via debugger command. |
Applications
| BLDC Motor Control | Industrial Touch Panel |
|---|---|
|
Use Scenario: Closed-loop 3-phase brushless DC motor drive in HVAC blowers or pump systems. IC Role / Device Role / Timing Role: Real-time commutation controller using FTM-generated PWM, ADC-sampled phase currents, and LPTMR-synchronized timing. Use Value: Hardware deadtime insertion and VLPS-mode ADC wakeup reduce software overhead and enable rapid fault response (<10 µs overcurrent shutdown). |
Use Scenario: Capacitive touch interface on factory HMIs exposed to ESD and conducted noise. IC Role / Device Role / Timing Role: Primary touch processor with dual TSI modules performing mutual capacitance scanning and shielded sensing. Use Value: 47-channel TSI with built-in digital filtering and noise rejection achieves >8 kV contact ESD immunity without external components. |
| Smart Sensor Node | Low-Power Telemetry Gateway |
|
Use Scenario: Battery-powered environmental monitor logging temperature, humidity, and vibration. IC Role / Device Role / Timing Role: System-on-chip sensor aggregator with ADC, CMP (for threshold alerts), and LPIT-triggered periodic wake. Use Value: VLPS mode draws <2.5 µA while maintaining ADC readiness and LPUART receive - extends 2xAA battery life to >5 years. |
Use Scenario: Edge gateway collecting Modbus RTU data from legacy PLCs and forwarding via LoRaWAN. IC Role / Device Role / Timing Role: Protocol bridge with LPUART×3 handling RS-485 interfaces and FlexIO emulating custom serial framing. Use Value: Three independent LPUARTs with DMA and VLPS wake allow concurrent polling of multiple slave devices without CPU load. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MKE17Z256VLL7 | 100-pin LQFP, 89 GPIOs, 50 TSI channels - larger package, higher I/O count, same core/peripherals. | Required when >58 GPIOs or >47 TSI channels needed; unsuitable for space-constrained 64-pin layouts. | Select MKE17Z256VLL7 only if board redesign accommodates 100-pin footprint and additional routing complexity. |
| MKE13Z256VLH7 | Same 64-pin LQFP, but reduced TSI (22 channels) and no temperature sensor - lower-cost variant in same family. | Suitable for non-touch applications or where thermal monitoring is not required; lacks TSI shielding capability. | Choose MKE13Z256VLH7 for cost-sensitive motor control without HMI, but verify TSI channel count suffices for target interface. |
Compared with MKE17Z256VLH7, the VLL7 offers greater I/O scalability at the cost of board area, while the MKE13Z256VLH7 trades TSI capability and thermal sensing for lower unit cost - both require validation of peripheral feature alignment before drop-in use.
Availability
MKE17Z256VLH7 is available at Aetrix Electronics and suitable for BLDC motor control, industrial HMI, and smart sensor node applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for MKE17Z256VLH7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in ARM-based microcontrollers and edge processing.
The Kinetis KE17Z series targets cost-sensitive, ultra-low-power industrial control applications - designed to deliver high analog integration, robust touch sensing, and seamless motor control in compact LQFP packages.
FAQ
What is the maximum operating frequency of the MKE17Z256VLH7?
The MKE17Z256VLH7 features an ARM Cortex-M0+ core rated for up to 72 MHz operation. This maximum frequency is achievable when powered within the specified 2.7–5.5 V supply range and operating within the –40 to 105 °C ambient temperature range. The system clock is derived from the SCG module using sources such as the 48 MHz FIRC or external crystal, with appropriate dividers configured in software. MKE17Z256VLH7 maintains full peripheral functionality at this speed, including ADC sampling at 1 Msps and FTM PWM generation.
Does the MKE17Z256VLH7 support hardware debugging during development?
Yes, the MKE17Z256VLH7 includes a Serial Wire Debug (SWD) interface compliant with ARM CoreSight standards, enabling full run-control, register inspection, memory access, and basic trace via Micro Trace Buffer (MTB). Debug is accessible through standard tools like MCUXpresso IDE and J-Link probes. Note that security can be enabled via flash configuration field 0x40E, which disables SWD memory access - MKE17Z256VLH7 retains debug port functionality for mass erase even when secured.
How many analog-to-digital converter channels does the MKE17Z256VLH7 provide?
The MKE17Z256VLH7 integrates one 12-bit successive approximation register (SAR) ADC module supporting up to 16 single-ended analog input channels. These channels are mapped to dedicated pins (e.g., ADC0_SE0 through ADC0_SE15) and can be triggered by hardware sources including FTM, LPTMR, LPIT, CMP output, or external pins. MKE17Z256VLH7 also includes an on-die temperature sensor connected to ADC channel AD26 for system thermal monitoring.
Can the MKE17Z256VLH7 operate in ultra-low-power modes while retaining peripheral functionality?
Yes, the MKE17Z256VLH7 supports Very Low Power Stop (VLPS) mode where the core and most peripherals are disabled, yet critical functions remain active: ADC, CMP, LPUART×3, LPSPI, LPI2C, LPIT, LPTMR, FlexIO, and DMA. These peripherals operate using SIRC or OSC clocks, enabling wake-on-event capabilities with sub-5 µs latency. MKE17Z256VLH7 achieves typical VLPS current draw of 2.5 µA - making it suitable for battery-powered applications requiring long-term standby with responsive wake behavior.
What touch sensing capability does the MKE17Z256VLH7 offer?
The MKE17Z256VLH7 includes two independent Touch Sense Interface (TSI) modules supporting a total of 47 touch channels - 25 on TSI0 and 22 on TSI1 - optimized for mutual capacitance scanning with shield channel support. Each TSI module provides hardware-accelerated noise filtering, automatic baseline tracking, and ESD-tolerant input structure. MKE17Z256VLH7's TSI implementation meets IEC 61000-4-2 Level 4 (±8 kV contact) without external protection components, making it ideal for rugged industrial touch panels.
MKE17Z256VLH7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 64-LQFP
- Series:
- Kinetis KE1xZ
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+
- Core Size:
- 32-Bit Single-Core
- Speed:
- 72MHz
- Connectivity:
- FlexIO, I2C, SPI, UART/USART
- Peripherals:
- DMA, LVD, PWM, WDT
- Number of I/O:
- 58
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 48K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 16x12b SAR; D/A 1x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
MKE17Z256VLH7 FAQ
1.How can I place an order for MKE17Z256VLH7 through Aetrix?
Please submit a Request for Quotation (RFQ) for MKE17Z256VLH7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MKE17Z256VLH7 reliable?
The price and inventory of MKE17Z256VLH7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MKE17Z256VLH7 is usually 5 days.
3.What payment methods are accepted for MKE17Z256VLH7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MKE17Z256VLH7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MKE17Z256VLH7?
MKE17Z256VLH7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MKE17Z256VLH7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MKE17Z256VLH7?
For technical support, including MKE17Z256VLH7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MKE17Z256VLH7 requirements.
6.How does Aetrix verify that MKE17Z256VLH7 is sourced from the original manufacturer or authorized distributors?
All MKE17Z256VLH7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MKE17Z256VLH7 meets industry standards.
7.What is the process for return or replacement of MKE17Z256VLH7?
All MKE17Z256VLH7 units undergo pre-shipment inspection (PSI). If there is an issue with MKE17Z256VLH7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MKE17Z256VLH7 part is unused and in its original packaging.
Return procedure for MKE17Z256VLH7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MKE17Z256VLH7 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

