onsemi MM80C97N

Overview

MM80C97N from Fairchild Semiconductor is a 3-STATE Hex Inverter IC with independent dual enable controls, designed for bidirectional bus interfacing in CMOS/TTL mixed-signal systems. It features six inverting buffers, 3.0V–15V supply range, 40 ns typical propagation delay into 150 pF at VCC = 10V, and high noise immunity (0.45 × VCC typ.), deployed in industrial control backplanes and legacy data acquisition subsystems.

For engineers reviewing the MM80C97N datasheet, pinout, applications, or equivalent options, key selection criteria include its dual 3-STATE control architecture (DIS1 for outputs Y1–Y2, DIS2 for Y3–Y6), TTL-compatible drive capability (1 TTL load), wide voltage operation, and PDIP-16 package compatibility with through-hole PCB assembly.

Technical Context

The MM80C97N implements six independent CMOS inverters with two logically separate 3-STATE output enable paths: DIS1 controls outputs Y1 and Y2, while DIS2 controls Y3 through Y6. Each inverter exhibits rail-to-rail output swing and input thresholds referenced to VCC (e.g., VIN(1) ≥ 3.5V at VCC = 5V).

Its dual-enable structure enables selective isolation of bus segments-such as isolating sensor interface lines (Y1–Y2) from processor-side data lanes (Y3–Y6)-without requiring external logic. Input protection includes diode clamps to VCC and GND, supporting ±2 kV HBM ESD robustness per JEDEC JESD22-A114.

Key Specifications

Pinout & Package

MM80C97N is housed in a 16-lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" wide, with 0.100" lead pitch and through-hole mounting. Pin 1 is marked by a notch or dot; pin numbering follows standard DIP convention (counterclockwise from top-left).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar hex inverter applications.

Compared with CD40107BE and 74HC240N, the MM80C97N uniquely delivers dual independent 3-STATE control within a 3–15V operating envelope-enabling selective bus segment isolation and mixed-voltage interoperability that neither alternative supports without redesign.

Availability

MM80C97N is available at Aetrix Electronics and suitable for industrial backplane bus drivers, legacy data acquisition interfaces, motor control logic isolators, and test equipment signal conditioning requiring stable component supply across extended temperature and voltage ranges.

Supply support for MM80C97N includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Fairchild Semiconductor was a U.S.-based semiconductor manufacturer specializing in analog, power, and interface ICs before its acquisition by ON Semiconductor in 2016.

The MM80C97N belongs to Fairchild's military- and industrial-grade 80C CMOS logic family, engineered for reliability in harsh environments with wide supply tolerance and robust ESD protection.

FAQ

What is the function of DIS1 and DIS2 on the MM80C97N?

DIS1 is the low-active enable input controlling outputs Y1 and Y2 only; DIS2 is the low-active enable input controlling outputs Y3 through Y6. When DIS1 is HIGH, Y1 and Y2 are in high-impedance state regardless of input states; similarly, DIS2 independently gates Y3–Y6. This dual-control architecture allows selective bus segment isolation. The MM80C97N datasheet confirms this split enable mapping in the truth table and schematic diagram.

Can the MM80C97N operate at 12V supply voltage?

Yes, the MM80C97N supports VCC from 3.0V to 15V, and all DC and AC specifications-including propagation delay (40 ns max at CL = 150 pF), output drive (±20 mA at VCC = 10V), and noise margin-are guaranteed across this full range. At 12V, it delivers enhanced noise immunity (0.45 × VCC ≈ 5.4V) and higher sink/source current than at 5V. The MM80C97N absolute maximum rating permits 18V, but operation above 15V is not characterized.

Is the MM80C97N pin-compatible with the MM80C95N or MM80C98N?

No, the MM80C97N is not pin-compatible with MM80C95N or MM80C98N. While all three share the same PDIP-16 package and pin count, their enable pin assignments differ: MM80C95N uses a single common DIS input (pin 13), MM80C97N uses DIS1 (pin 12) and DIS2 (pin 14), and MM80C98N uses DIS1 (pin 12) and DIS2 (pin 14) but with inverted logic polarity per truth table. Swapping them without board revision will cause functional failure. The MM80C97N connection diagram explicitly defines its unique dual-enable pinout.

Does the MM80C97N require external pull-up resistors on its outputs?

No, the MM80C97N does not require external pull-up resistors because it features push-pull CMOS outputs capable of actively driving both logic HIGH and LOW states. Its outputs switch rail-to-rail (e.g., 0.5V/4.5V at VCC = 5V) and provide ±4.35 mA drive strength-sufficient to directly interface with TTL loads. Pull-ups are unnecessary unless implementing wired-OR logic, which contradicts the MM80C97N's 3-STATE architecture. The MM80C97N schematic diagram shows no open-drain topology.

What is the maximum capacitive load the MM80C97N can drive while maintaining specified timing?

The MM80C97N AC specifications are characterized up to 150 pF load capacitance, with propagation delay guaranteed at 40 ns max (VCC = 10V, CL = 150 pF). Driving loads beyond 150 pF increases delay nonlinearly-e.g., at 300 pF, typical delay exceeds 100 ns per the "Propagation Delay vs Load Capacitance" curve in the MM80C97N datasheet. For reliable timing closure, keep total net capacitance ≤150 pF using controlled impedance routing and minimal stub lengths.