Monolithic Power Systems Inc. MP100LGN-P

Overview

MP100LGN-P from Monolithic Power Systems is an inductor-less offline AC/DC regulator IC designed for low-power bias supply in off-line applications. It accepts universal AC input (85–305 VAC), delivers adjustable DC output (1.5–15 V) up to 220 mA, achieves <100 mW standby power, and integrates thermal shutdown, OVP, SCP, and power-good signaling. It serves as a compact primary-side bias rail for wireless control modules and wall-mounted smart switches.

For engineers reviewing the MP100LGN-P datasheet, MP100LGN-P pinout, MP100LGN-P application, or MP100LGN-P equivalent, key selection criteria include its inductor-less architecture, VD capacitor-based energy transfer, 245 µs power-good delay, 12 V typical regulated output, and SOIC-8 EP thermal pad layout requirements.

Technical Context

The MP100LGN-P implements a proprietary smart-charging architecture that samples AC line voltage only within a narrow "charging window" (31.5–34 V), enabling ultra-low quiescent current (20–40 µA) and <100 mW no-load consumption. Its internal NMOS switch features controlled slew rates (130–200 µs/A) to meet conducted EMI standards with only a 220 nF X-capacitor.

Regulation is achieved via a two-stage topology: first, VIN charges the external VD capacitor through a slow-turn-on/off switch; second, an integrated LDO stage (VB→VOUT) delivers stable output with 0.1% line regulation and 0.3% load regulation. Protection logic includes auto-restart over-current, active bleeder discharge below 14.4 V VD, and thermal shutdown at 160°C with 20°C hysteresis.

Key Specifications

Pinout & Package

MP100LGN-P is housed in an SOIC-8 EP (exposed pad) package. The exposed thermal pad must be soldered to a large GND copper area to achieve θJA = 50°C/W and sustain 2.5 W continuous dissipation at +25°C ambient.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar offline inductor-less regulator applications.

Compared with MP101LGN-P, MP100LGN-P trades minor output accuracy for lower cost and broader availability; versus LNK3206P, it eliminates transformer dependency and reduces layout footprint by >40%, making it ideal for space-constrained, non-isolated, sub-250 mW applications.

Availability

MP100LGN-P is available at Aetrix Electronics and suitable for wall switches, Zigbee/Z-Wave modules, and low-power standby rails requiring stable component supply, RoHS-compliant packaging, and long-term industrial lifecycle support.

Supply support for MP100LGN-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and manufacturing partners qualified to ISO 9001 and IATF 16949 standards.

The MP100LGN-P belongs to MPS's EasyPower™ offline regulator product line, engineered specifically for ultra-low-standby, inductor-less AC/DC conversion in smart home, IoT, and industrial control applications where size, cost, and regulatory compliance are critical.

FAQ

What is the minimum VD capacitor value required for stable 12 V/20 mA operation?

A 4.7 µF/50 V ceramic capacitor is the minimum recommended value for VD when operating at 12 V/20 mA with full-wave rectification. For improved ripple suppression and thermal margin, combine it with a 220 µF/35 V aluminum electrolytic capacitor in parallel-this ensures VD remains above 15.4 V during discharge and maintains LDO enablement under worst-case line and load conditions.

Can MP100LGN-P operate with half-wave rectification?

Yes, MP100LGN-P supports both full-wave and half-wave rectification. With half-wave input, the VD capacitor must be doubled (e.g., 10 µF minimum) to maintain equivalent energy delivery per cycle, and maximum output power drops by ~50% due to reduced charging opportunities per AC period-designers should verify thermal rise and output ripple using the τ = 20 ms factor in the VD capacitance equation.

How does the active bleeder circuit affect no-load efficiency?

The active bleeder draws 180–360 µA only when VD falls below 14.4 V, which occurs intermittently during light/no-load conditions. This adds <1.5 mW to total no-load power-well within the <100 mW specification-and ensures reliable restart by discharging parasitic VIN-to-GND capacitance, preventing false UVLO lockout after AC interruption.

Is an external MOV required for surge protection?

Yes-an external MOV (e.g., 275 VAC rated) is mandatory between L/N and GND. Because MP100LGN-P lacks a bulk input capacitor, it cannot absorb line transients; the MOV clamps surges before they reach VIN, protecting the internal 700 V-rated switch. Combined with a 20 Ω fuse resistor and grounded thermal pad, this configuration passes IEC 61000-4-5 Level 3 (2 kV line-earth).

What is the impact of NC pin (Pin 7) misconnection?

Pin 7 is not internally bonded and must remain unconnected. If accidentally shorted to GND, VOUT, or VIN, it may create unintended parasitic paths that degrade EMI performance, increase leakage current, or cause intermittent startup failure-PCB layout must enforce keep-out zone and avoid routing traces or vias near Pin 7.

Does MP100LGN-P support adjustable soft-start?

No-MP100LGN-P has fixed internal soft-start behavior tied to VD voltage ramp. The LDO enables only when VD reaches 15.4 V, and PG asserts 245 µs later; there is no external soft-start pin or programmable delay. For systems requiring longer sequencing delays, add a simple RC network on the PG output to extend the logic assertion time.

How does thermal pad connection affect reliability?

Soldering the exposed thermal pad to a ≥100 mm² GND copper pour reduces θJA from 50°C/W to ≤35°C/W, lowering junction temperature by up to 30°C at full load. This extends lifetime by 2× per 10°C reduction (per Arrhenius model) and improves surge immunity by providing low-impedance path for transient currents during ESD or lightning events.