Monolithic Power Systems Inc. MP111DS-LF-P

Overview

MP111DS-LF-P from Monolithic Power Systems is a dedicated dying gasp storage and release control IC that manages energy backup during AC/DC input failure in broadband access equipment. It charges an external storage capacitor to a user-programmable voltage (up to 32 V), monitors VIN, and dumps up to 2.5 A into the input rail when VIN drops below a programmable release threshold (e.g., 10.2 V). It features built-in 250 mA charging current limit, open-drain GASP flag output, and operates across 4.5–18 V input.

For engineers reviewing the MP111DS-LF-P datasheet, MP111DS-LF-P pinout, MP111DS-LF-P application, or MP111DS-LF-P equivalent, key selection criteria include programmable storage/release voltage thresholds, 2.5 A dump current capability, SOIC-8 thermal performance (θJA = 90°C/W), GASP flag timing (2 µs delay), and compatibility with standard electrolytic storage capacitors in DSL/PON modem hold-up designs.

Technical Context

The MP111DS-LF-P implements a two-phase storage management architecture: pre-charge (inrush-limited to 250 mA) followed by regulated boost charging via the BST pin connected to a DC/DC switch node. It uses dual feedback loops-FB1 for storage voltage regulation and FB2 for release voltage detection-with independent hysteresis (50 mV for FB1, 350 mV for VIN UVLO).

During power loss, it activates a high-current discharge path from STRG to VIN, sustaining regulated input voltage at the release threshold for up to hundreds of milliseconds depending on storage capacitance and load. The GASP pin provides TTL-compatible status signaling with 1.05×VFB2 high threshold and 1.00×VFB2 low threshold, enabling system-level power-fail response coordination.

Key Specifications

Pinout & Package

The MP111DS-LF-P is housed in a standard SOIC-8 package (5.0 mm × 6.2 mm, 1.27 mm pitch) with exposed pad not present; thermal performance relies on copper area and vias per JEDEC MS-012 AA.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dying gasp control applications.

Compared with MPQ111DS-AEC1-LF-Z, the MP111DS-LF-P offers identical functionality at lower cost and qualification overhead for commercial infrastructure; versus TPS65235-1RGET, it delivers higher dump current and full voltage programmability but requires external DC/DC and more BOM components.

Availability

MP111DS-LF-P is available at Aetrix Electronics and suitable for cable modem power fail response, DSL gateway brownout hold-up, PON ONU power loss signaling, and small-cell backhaul link preservation requiring stable component supply and long-term lifecycle support.

Supply support for MP111DS-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP111 belongs to MPS's broadband infrastructure power management product line, engineered specifically to extend hold-up time and enable reliable power-fail signaling in DSL, PON, and cable access equipment operating from 4.5–18 V rails.

FAQ

What is the maximum recommended storage capacitor voltage for MP111DS-LF-P?

The absolute maximum VSTRG rating is 32 V, but the recommended operating range is VIN to (2×VIN − 0.8 V), capped at 32 V. For a 12 V input, 23 V storage (as shown in the typical application) is optimal-enabling use of 25 V-rated electrolytics with >90% voltage derating, which improves lifetime and reduces size versus lower-voltage alternatives.

How does the MP111DS-LF-P prevent overcharging the storage capacitor?

The MP111DS-LF-P uses closed-loop regulation via the FB1 pin: when the STRG voltage reaches the value set by the R1/R2 divider (e.g., 23 V), the internal charge pump disables, and the BST path opens. A small refresh current then maintains voltage within ±50 mV hysteresis, eliminating continuous charging and minimizing capacitor stress.

Can the GASP pin drive an LED directly without a buffer?

No. The GASP pin is an open-drain output rated for 4 mA sink current at 0.4 V drop. Driving even a low-current LED (e.g., 2 mA @ 1.8 V) would require ~1.4 V headroom, exceeding its capability. A pull-up to VIN and external NPN/MOSFET buffer is required for LED or logic-level interface beyond microcontroller GPIO.

What is the purpose of the VMAX pin and why is a 2.2 nF capacitor required?

VMAX supplies the internal LDO that powers control logic and comparators independently of VIN fluctuations. The 2.2 nF ceramic capacitor stabilizes this rail against switching noise from the BST-driven charge pump and ensures accurate FB1/FB2 reference tracking during dynamic events like dump initiation.

Is the MP111DS-LF-P compatible with non-isolated DC/DC converters?

Yes-the BST pin must connect to the switch node (SW) of *any* DC/DC converter capable of generating sufficient voltage headroom (≥VIN + 5 V) to charge the storage capacitor above VIN. It works with buck, boost, or buck-boost topologies, provided SW node voltage swing exceeds the target storage voltage during boost phase.

How is thermal performance affected by PCB layout in SOIC-8?

θJA = 90°C/W assumes a 4-layer JEDEC-standard test board. In practice, adding ≥2 cm² of 2-oz copper connected to GND pins (4 and 5) with ≥6 thermal vias reduces θJA by ~25–30°C/W. Poor layout-such as narrow traces to GND or missing VMAX decoupling-causes premature thermal shutdown during sustained 2.5 A dump operation.