Monolithic Power Systems Inc. MP174AGS-Z

Overview

MP174AGS-Z from Monolithic Power Systems is a 700V primary-side constant-voltage (CV) regulator with integrated MOSFET, supporting buck, buck-boost, boost, and flyback topologies in non-isolated off-line power supplies. It delivers up to 400mA output current in CCM mode, achieves <30mW no-load consumption, and features frequency foldback and peak-current compression for high light-load efficiency - deployed in home appliance standby power and white-goods auxiliary supplies.

For engineers reviewing the MP174AGS-Z datasheet, MP174AGS-Z pinout, MP174AGS-Z application, or MP174AGS-Z equivalent, key selection criteria include its 700V/13.5Ω integrated MOSFET, VCC UVLO thresholds (5.1–5.3V turn-on, 5.4–5.6V turn-off), 2.55V FB reference, thermal shutdown at 150°C, and SOIC-8 package compatibility with board-level EMI mitigation requirements.

Technical Context

The MP174AGS-Z implements primary-side regulation using internal error amplifier sampling 6μs after MOSFET turn-off, referenced to a 2.55V precision bandgap. Its green-mode operation dynamically scales switching frequency and peak current limit (660mA typ.) downward under light load via off-time extension and ramp-based peak-current compression.

Protection logic includes auto-restart OLP triggered by FB voltage dropping below 1.7V for ≥220ms, SCP activation at 750–900mA with 180ns blanking, open-loop detection at FB <0.5V, and OTP recovery hysteresis of 30°C. The IC self-starts from drain via internal HV regulator and maintains VCC bias with external capacitor discharge/recharge cycles during faults.

Key Specifications

Pinout & Package

MP174AGS-Z is housed in an industry-standard SOIC-8 package with exposed pad for thermal enhancement. Pin functions are validated per MPS datasheet Rev. 1.0 (2019), with pins 5, 6, and 8 designated as no-connect (N/C). The package supports standard reflow profiles and meets RoHS, halogen-free, and lead-free requirements.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar primary-side CV regulator applications.

Compared with MP174AGS-Z, MP173AGS-Z trades EMI and no-load efficiency for lower unit cost and simpler compensation, while LNK3206G adds secondary feedback complexity and size to achieve tighter regulation and higher surge robustness - making MP174AGS-Z optimal for cost-sensitive, space-constrained, globally rated standby supplies.

Availability

MP174AGS-Z is available at Aetrix Electronics and suitable for home appliance auxiliary supplies, white-goods standby power, and industrial control panel PSUs requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.

Supply support for MP174AGS-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and manufacturing partners qualified to AEC-Q200 and ISO 9001 standards.

The MP174A product line targets cost-sensitive, non-isolated off-line regulators for consumer and industrial applications where optocoupler elimination, ultra-low standby power, and integrated 700V MOSFETs deliver system-level BOM and layout simplification.

FAQ

What is the maximum recommended output power for MP174AGS-Z in SOIC-8 package?

The MP174AGS-Z supports up to 5W output power in continuous conduction mode when thermally managed on a 4-layer PCB with θJA = 96°C/W. At ambient temperatures above 50°C, derating is required per PD(MAX) = (150°C − TA)/96°C/W; sustained operation above 1W at TA > 70°C requires copper pour or heatsink augmentation.

Can MP174AGS-Z operate in flyback topology with primary-side regulation?

Yes - MP174AGS-Z supports flyback topology with primary-side regulation using a transformer with auxiliary winding for feedback sampling. The FB pin senses reflected output voltage via RC network; no optocoupler is needed. Design requires careful transformer turns ratio selection to ensure FB stays within 0.4–2.65V range across line/load conditions.

How does the MP174AGS-Z achieve <30mW no-load consumption?

It combines three mechanisms: frequency foldback (reducing switching frequency under light load), peak-current compression (scaling peak current limit downward as off-time increases), and low VCC operating current (200μA in no-switching state). These are coordinated by internal green-mode control logic that minimizes energy per cycle without compromising regulation stability.

What is the purpose of the N/C pins (5, 6, 8) in SOIC-8 package?

Pins 5, 6, and 8 are internally unconnected and must remain floating - no routing, soldering, or grounding is permitted. Connecting them risks parasitic coupling, EMI degradation, or latch-up due to proximity to high-dv/dt DRAIN node. Layout guidelines require keeping these pins clear of traces and copper pours.

Does MP174AGS-Z require an external startup resistor?

No - MP174AGS-Z integrates a high-voltage startup current source connected to the DRAIN pin, enabling self-biasing from rectified AC input. An external startup resistor is unnecessary; however, a small VCC capacitor (≥1μF ceramic) is mandatory to sustain control circuitry during normal operation and fault recovery cycles.

How is open-loop detection implemented and what triggers it?

Open-loop detection activates when FB voltage falls below 0.5V (typical) for >512 switching cycles post-soft-start. This indicates loss of feedback signal - e.g., open feedback resistor or disconnected sampling capacitor. The IC shuts down and initiates automatic restart after VCC discharges to 2.4V, ensuring fail-safe behavior without external supervision.

What layout practices minimize EMI in MP174AGS-Z designs?

Minimize high-di/dt loop area (DRAIN–SOURCE–inductor–diode), place 100–470pF capacitor between FB and SOURCE near the IC, use solid ground plane under SOURCE pins, connect exposed pad to DRAIN net for thermal relief, and keep FB trace short/shielded from noisy nodes like DRAIN and switching node.