Monolithic Power Systems Inc. MP18831-A4BGLU-P

Overview

MP18831-A4BGLU-P from Monolithic Power Systems is an isolated dual-input high-side/low-side half-bridge gate driver with 4A peak source/sink current, 50ns typical propagation delay, and configurable dead time via external resistor. It uses capacitive isolation for 5kVRMS input-to-output withstand voltage (SOIC-16 WB), supports 2.8–5.5V primary-side VDDI and up to 30V secondary-side supply, and targets isolated DC/DC and AC/DC converters requiring robust CMTI >100kV/µs.

For engineers reviewing the MP18831-A4BGLU-P datasheet, MP18831-A4BGLU-P pinout, MP18831-A4BGLU-P application, or MP18831-A4BGLU-P equivalent, this device delivers verified functional isolation between secondary-side drivers (1500VDC in SOIC-16 NB/WB), overlap protection, UVLO options per channel (5V threshold), and LGA-13 (5mm×5mm) package compatibility with traceable thermal derating curves.

Technical Context

The MP18831-A4BGLU-P implements a dual-channel isolated architecture where each output driver (OUTA/VSSA/VDDA and OUTB/VSSB/VDDB) operates on independent grounds, enabling flexible half-bridge configuration with programmable dead time (10–1100ns) set by an external resistor on the DT pin. Its capacitive isolation barrier provides reinforced insulation (UL 1577, VDE 0884-17) and guarantees CMTI >100kV/µs under 1500V common-mode transients.

Control logic accepts TTL/CMOS-compatible inputs (INA/INB) with internal pull-downs, while enable/disable is supported via EN (pull-high default) or DIS (pull-low default) pins-both referenced to GNDI. The device integrates independent under-voltage lockout on all supply rails (VDDI, VDDA, VDDB), with the -A4B variant specifying 5V UVLO thresholds on secondary-side supplies.

Key Specifications

Pinout & Package

The MP18831-A4BGLU-P is packaged in LGA-13 (5mm × 5mm) with exposed pad, optimized for thermal performance and board space efficiency. Pin numbering follows top-view orientation with GNDI (Pin 4), INA (Pin 2), INB (Pin 3), EN/DIS (Pins 5/5), DT (Pin 6), VDDA (Pin 13), VSSA (Pin 11), OUTA (Pin 12), VDDB (Pin 10), VSSB (Pin 8), and OUTB (Pin 9). Pins 1, 7, and 13 are NC.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar isolated half-bridge gate driver applications.

Compared with Si823H4BB-IS and ADuM4223BRIZ, the MP18831-A4BGLU-P uniquely combines independently configurable dead time, dual-rail UVLO, and matched 4A drive strength across two fully isolated secondary domains-making it optimal for high-reliability isolated converters demanding timing precision and fault resilience.

Availability

MP18831-A4BGLU-P is available at Aetrix Electronics and suitable for isolated DC/DC converters, offline AC/DC adapters, and solar microinverters requiring stable component supply with guaranteed long-term manufacturability and RoHS-compliant packaging.

Supply support for MP18831-A4BGLU-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, including DC/DC converters, LED drivers, and isolated gate drivers, with global manufacturing and quality certifications.

The MP18831 product line delivers isolated half-bridge gate drivers optimized for high-efficiency, high-density power conversion in industrial, telecom, and renewable energy systems-designed to replace optocoupler-based solutions with higher speed, reliability, and integration.

FAQ

What is the isolation voltage rating for MP18831-A4BGLU-P?

The MP18831-A4BGLU-P, in its LGA-13 package, is certified for 2.5kVRMS isolation (60s, UL 1577) and 3535VPK per DIN EN IEC 60747-17. This corresponds to a maximum working voltage of 400VRMS and qualifies it for reinforced insulation in systems up to 480VP under GB 4943.1-2011.

How is dead time configured on MP18831-A4BGLU-P?

Dead time is set by connecting an external resistor (2–150kΩ) between the DT pin (Pin 6) and GNDI. Typical values yield 130–1100ns dead time; adding ≥220pF ceramic capacitance in parallel improves noise immunity. Leaving DT open sets minimum dead time (~10ns).

Does MP18831-A4BGLU-P support independent enable/disable control per channel?

No-it provides global enable/disable via EN (active-high) or DIS (active-low) pins affecting both OUTA and OUTB simultaneously. Channel-specific control is achieved through INA and INB inputs, which remain functional during enable states but are ignored when disabled.

What are the UVLO thresholds for VDDA and VDDB on the -A4B variant?

The MP18831-A4BGLU-P specifies a 5V UVLO threshold on both VDDA and VDDB rails, with 300mV hysteresis (5.0V ±0.3V). This ensures gate drive ceases before secondary supply falls below the minimum required for reliable MOSFET enhancement.

Can MP18831-A4BGLU-P drive GaN HEMTs effectively?

Yes-the 4A peak source/sink current, <20ns rise/fall times (with 1.8nF load), and 50ns propagation delay enable direct drive of low-Qg GaN devices like EPC2065 or GS66508T without external buffers, provided gate loop inductance is minimized and layout adheres to high-speed guidelines.

What thermal derating applies to MP18831-A4BGLU-P in LGA-13 package?

In LGA-13, the MP18831-A4BGLU-P has θJA = 106°C/W. At 125°C junction, maximum ambient is 100°C for full 1175mW safety power; above that, linear derating applies-e.g., at 110°C ambient, max power drops to ~1000mW per published curves.

Is there functional isolation between the two secondary-side drivers?

Yes-1500VDC functional isolation is specified between VSSA and VSSB in SOIC-16 NB/WB packages; in LGA-13, it is 700VDC. This allows independent grounding of HS and LS drivers in asymmetric or floating topologies such as dual-active bridge or three-level NPC inverters.