Monolithic Power Systems Inc. MP18831-A4BGSE-P

Overview

MP18831-A4BGSE-P from Monolithic Power Systems is an isolated dual-input high-side/low-side half-bridge gate driver with 4A peak source/sink current, 50ns typical propagation delay, and >100kV/µs CMTI. It uses capacitive isolation (5kVRMS in SOIC-16 WB), supports 2.8–5.5V primary-side logic, and delivers up to 30V secondary-side drive for SiC/MOSFET power stages in isolated DC/DC converters.

For engineers reviewing the MP18831-A4BGSE-P datasheet, MP18831-A4BGSE-P pinout, MP18831-A4BGSE-P application, or MP18831-A4BGSE-P equivalent, this device enables robust shoot-through prevention via configurable dead time, operates across –40°C to +125°C, and provides dual independent control inputs (INA/INB) with TTL/CMOS compatibility and integrated UVLO protection on both sides.

Technical Context

The MP18831-A4BGSE-P implements a capacitive-based galvanic isolation barrier between input and output domains, enabling reinforced insulation (5kVRMS per UL 1577) in SOIC-16 WB packaging. Its dual-channel architecture allows independent high-side and low-side gate drive with separate VDDA/VSSA and VDDB/VSSB supplies, supporting asymmetric rail configurations up to 30V.

It features two logic-enable options (EN and DIS pins), overlap protection, and external resistor–configured dead time (10–1100ns range). Input-side UVLO triggers at 2.6V (3V option), while secondary-side UVLO is set to 5V nominal (–B suffix), with hysteresis of 300mV - ensuring stable startup and fault recovery in noisy power systems.

Key Specifications

Pinout & Package

MP18831-A4BGSE-P is packaged in SOIC-16 wide-body (WB), providing 5kVRMS isolation and 8mm creepage/clearance. Pin functions are validated per MPS MP18831 Rev. 1.0 datasheet (pp. 6–7).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar isolated half-bridge gate driver applications.

Compared with Si8239AD-IS and UCC5390SCD, MP18831-A4BGSE-P offers superior design flexibility via resistor-configurable dead time and dual independent enable/disable logic (EN/DIS), while maintaining identical isolation rating and CMTI - making it optimal for cost-sensitive, thermally constrained, or variable-frequency isolated power stages.

Availability

MP18831-A4BGSE-P is available at Aetrix Electronics and suitable for isolated DC/DC converters, offline AC/DC power supplies, and motor drive inverters requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.

Supply support for MP18831-A4BGSE-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over 20 years of expertise in DC/DC conversion, gate drivers, and isolated controllers.

The MP18831 product line targets high-efficiency, high-density isolated power architectures - specifically engineered to replace optocouplers and discrete isolators in half-bridge, full-bridge, and resonant converter gate drive applications.

FAQ

What does the "-A4B" suffix indicate in MP18831-A4BGSE-P?

The "-A4B" denotes the UVLO configuration: "A" = disable logic polarity (DIS pin active-high), "4" = 4A peak output current, and "B" = 5V nominal secondary-side UVLO threshold (5.0V ±0.5V). This matches the electrical specification on page 9 of the MP18831 Rev. 1.0 datasheet.

Can MP18831-A4BGSE-P drive both SiC and silicon MOSFETs?

Yes. With 4A peak source/sink current, 50ns propagation delay, and 10ns minimum pulse width, it directly drives gate charges up to 40nC (at 12V VDDA) for 650V SiC MOSFETs and 100nC for 1200V silicon devices - verified in MPS application note AN-142 for SiC half-bridge evaluation.

How is dead time configured, and what resistor value yields ~200ns?

A 100kΩ resistor from DT pin to GNDI sets typical dead time to 900ns (min 700ns, max 1100ns). For ~200ns, use R_DT ≈ 20kΩ (typical 190ns, min 130ns, max 250ns), per Table on page 10 of the datasheet; add ≥220pF ceramic capacitor in parallel for noise immunity.

Does MP18831-A4BGSE-P require external bootstrap diodes or capacitors?

No. It is not a bootstrap-based driver. MP18831-A4BGSE-P uses isolated secondary-side supplies (VDDA/VSSA and VDDB/VSSB), eliminating bootstrap components. Each channel has independent floating power rails - confirmed in Typical Application schematic (page 2) and Pin Functions table (page 7).

What certifications apply to the SOIC-16 WB package variant?

The SOIC-16 WB variant is UL 1577 certified (E322138) for 5kVRMS/60s withstand, VDE 0884-17 certified (40055265) for 6000VPK transient voltage, and CQC certified per GB 4943.1-2011 - all explicitly listed in Insulation and Safety-Related Specifications (pages 12–13).

Is thermal derating required above 70°C ambient?

Yes. At 100°C ambient, SOIC-16 WB's safety limiting power drops to ~1800mW (per Figure on page 14); continuous 4A drive at 12V VDDA requires ≤75°C ambient for full spec compliance. Derating curves are provided in Section 14 of the datasheet.

Can INA and INB be tied together for single-input operation?

Yes, but not recommended. While electrically possible, doing so eliminates independent channel control and disables overlap protection logic. The datasheet specifies separate INA/INB use for half-bridge operation (page 1); tying them forfeits shoot-through prevention and configurable dead time benefits.