Monolithic Power Systems Inc. MP18831-A4BGY-P

Overview

MP18831-A4BGY-P from Monolithic Power Systems is an isolated dual-input high-side/low-side half-bridge gate driver with 4A peak source/sink current, 50ns typical propagation delay, and >100kV/µs CMTI. It features configurable dead time via external resistor, 2.8–5.5V primary-side VDDI, and up to 30V secondary-side supply-designed for robust switching control in isolated DC/DC converters.

For engineers reviewing the MP18831-A4BGY-P datasheet, MP18831-A4BGY-P pinout, MP18831-A4BGY-P application, or MP18831-A4BGY-P equivalent, key selection criteria include its SOIC-16 WB package (5kVRMS isolation), UVLO threshold of 5V (–B variant), dual independent input logic (INA/INB), and overlap protection architecture enabling safe half-bridge operation in high-noise power systems.

Technical Context

The MP18831 employs capacitive-based isolation to achieve reinforced insulation (UL 1577, VDE 0884-17) between primary and secondary sides, supporting functional separation of control and power grounds. Its dual-channel architecture allows independent high-side and low-side gate drive with separate VDDA/VSSA and VDDB/VSSB supplies, enabling asymmetric rail configurations.

Dead time is externally set via a resistor on the DT pin (2–150kΩ), yielding programmable delays from 10ns to 1.1µs with <10ns matching between channels. Input logic accepts TTL/CMOS levels (1.6V high threshold, 1.2V low threshold), and both EN and DIS pins provide redundant enable/disable control with internal pull-up (EN) and pull-down (DIS) resistors.

Key Specifications

Pinout & Package

MP18831-A4BGY-P is housed in a SOIC-16 wide-body (WB) package with 1.27mm pitch, 10.3mm × 7.5mm footprint, and reinforced insulation barrier. Pin 1 is marked with a dot; pins 3 and 8 are internally shorted VDDI inputs; pins 7 and 12 are NC.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar isolated half-bridge gate driver applications.

Compared with Si8239AD-IS and ADUM4223BRIZ, MP18831-A4BGY-P uniquely combines 4A drive, 50ns delay, and resistor-programmable dead time in a single SOIC-16 WB package-enabling higher power density and simplified timing design in isolated bridge topologies.

Availability

MP18831-A4BGY-P is available at Aetrix Electronics and suitable for isolated DC/DC converters, offline AC/DC power supplies, and solar microinverters requiring stable component supply, long-term lifecycle support, and certified safety isolation.

Supply support for MP18831-A4BGY-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over two decades of expertise in DC/DC conversion, motor drivers, and isolated gate drivers.

The MP18831 belongs to MPS's isolated gate driver product line, engineered specifically for high-efficiency, high-density isolated power stages-including LLC, phase-shifted full-bridge, and SiC/GaN-based converters-where timing precision, noise immunity, and safety certification are critical.

FAQ

What is the UVLO threshold for VDDA and VDDB on MP18831-A4BGY-P?

The "–B" suffix indicates a 5V nominal UVLO threshold for both VDDA and VDDB, with a typical value of 5.5V and hysteresis of 300mV. This ensures gate drive remains disabled until secondary-side supplies stabilize above 5V, preventing partial turn-on of power devices during startup or fault recovery.

Can MP18831-A4BGY-P drive both high-side and low-side switches in a single half-bridge configuration?

Yes. The device integrates two fully isolated output channels (OUTA/VDDA/VSSA and OUTB/VDDB/VSSB), allowing OUTA to drive the high-side switch (referenced to floating VSSA) and OUTB to drive the low-side switch (referenced to VSSB), with independent INA and INB inputs enabling true half-bridge control.

How is dead time configured on MP18831-A4BGY-P?

Dead time is set by connecting a resistor (2kΩ to 150kΩ) between the DT pin and GNDI. A 220pF ceramic capacitor in parallel is recommended for noise immunity. With R_DT = 20kΩ, typical dead time is 190ns; with R_DT = 100kΩ, it rises to 900ns. Matching between channels is within 10ns.

Does MP18831-A4BGY-P require external Miller clamps?

No. The MP18831 does not integrate active Miller clamps. However, its 4A sink capability and fast 50ns propagation delay minimize Miller-induced shoot-through risk. For IGBTs or high-Qg MOSFETs in noisy environments, external clamping diodes or RC networks may still be advised per layout and application requirements.

What safety certifications apply to the SOIC-16 WB package of MP18831-A4BGY-P?

MP18831-A4BGY-P (SOIC-16 WB) is UL 1577 certified for 5kVRMS isolation (60s), VDE 0884-17 certified for 6000VPK reinforced insulation, and CQC certified per GB 4943.1-2011. It supports up to 630VRMS working voltage and passes 125°C thermal cycling per safety standards.

Is there a difference between EN and DIS pins in functional behavior?

EN is active-high with internal 200kΩ pull-up; DIS is active-low with internal 200kΩ pull-down. Both pins disable outputs when asserted, but they serve complementary roles: EN enables default operation (open or high), while DIS provides fail-safe shutdown (open or low). Using both allows redundancy in safety-critical systems.

What is the maximum recommended switching frequency for MP18831-A4BGY-P?

While not explicitly limited, the 50ns propagation delay, 20ns rise/fall times, and 35ns minimum pulse width support reliable operation up to 1MHz in hard-switched topologies. In resonant converters (e.g., LLC), practical limits are determined by gate charge, layout, and thermal management-not driver bandwidth.