Monolithic Power Systems Inc. MP18831-A4CGSE-P

Overview

MP18831-A4CGSE-P from Monolithic Power Systems is an isolated dual-input high-side/low-side half-bridge gate driver with 4A peak source/sink current, 50ns typical propagation delay, and configurable dead time via external resistor. It delivers 5kVRMS isolation (SOIC-16 WB), >100kV/µs CMTI, and operates across –40°C to +125°C for use in isolated DC/DC converters driving SiC or GaN power stages.

For engineers reviewing the MP18831-A4CGSE-P datasheet, MP18831-A4CGSE-P pinout, MP18831-A4CGSE-P application, or MP18831-A4CGSE-P equivalent, this device supports TTL/CMOS-compatible 2.8–5.5V primary-side logic, 30V secondary-side drive supply, UVLO options down to 3V, and shoot-through prevention via overlap protection - critical for high-efficiency, high-density isolated power designs.

Technical Context

The MP18831-A4CGSE-P implements capacitive-based galvanic isolation between input and dual-output channels, enabling independent grounding of high-side and low-side drivers. Its dual-channel architecture supports half-bridge topologies with separate VDDA/VSSA and VDDB/VSSB supplies, each with dedicated UVLO thresholds set by the "A4C" suffix (3V UVLO).

Dead time is externally configured via a resistor on the DT pin (2–150kΩ), yielding 10–1100ns range with <10ns matching tolerance. Propagation delay matching (≤6ns) and pulse-width distortion (≤6ns) ensure precise timing control essential for synchronous switching in resonant LLC and phase-shifted full-bridge converters.

Key Specifications

Pinout & Package

MP18831-A4CGSE-P is supplied in SOIC-16 wide-body (WB) package, providing 5kVRMS isolation and 6000VPK reinforced insulation per VDE 0884-17. Pin functions are validated per MPS MP18831 Rev. 1.0 datasheet (pp. 7–8).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar isolated half-bridge gate driver applications.

Compared with Si823H4BD-IS and ADUM4223BRIZ, MP18831-A4CGSE-P uniquely combines adjustable dead time, 3V UVLO, and >100kV/µs CMTI in a single SOIC-16 WB package - making it optimal for high-density, high-reliability SiC/GaN power stages requiring design flexibility and noise immunity.

Availability

MP18831-A4CGSE-P is available at Aetrix Electronics and suitable for isolated DC/DC converters, offline AC/DC power supplies, and industrial motor drives requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for MP18831-A4CGSE-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, including DC/DC converters, LED drivers, and isolated gate drivers.

The MP18831 product line delivers isolated half-bridge gate drivers optimized for high-efficiency, high-power-density applications such as server PSUs, EV chargers, and industrial inverters - emphasizing robustness, timing precision, and safety certification.

FAQ

What does the "A4C" suffix indicate in MP18831-A4CGSE-P?

The "A4C" denotes the UVLO threshold configuration: "A" specifies active-enable logic (EN pin), "4" indicates 4A peak output current, and "C" sets the output-side UVLO to 3V (min 2.7V, typ 3.2V, max 3.7V). This enables reliable startup with low-voltage auxiliary supplies in multi-output converters.

Can MP18831-A4CGSE-P drive both high-side and low-side GaN FETs simultaneously?

Yes. Its dual isolated outputs (VDDA/VSSA and VDDB/VSSB) allow independent grounding - enabling direct drive of high-side and low-side GaN FETs in half-bridge configurations without bootstrap diodes or level shifters. Each channel delivers 4A peak current into 1.8nF load with 10–20ns rise/fall times.

What is the minimum dead time achievable with the DT pin open?

With the DT pin left unconnected (open), the dead time is minimized to 10–30ns (typ 20ns). This setting is suitable for high-frequency resonant topologies like LLC where minimal dead time reduces conduction losses while maintaining shoot-through immunity via hardware overlap protection.

Does MP18831-A4CGSE-P require external bootstrap capacitors?

No. Unlike non-isolated bootstrap drivers, MP18831-A4CGSE-P uses galvanic isolation to provide independent VDDA/VSSA and VDDB/VSSB supplies - eliminating the need for bootstrap diodes or capacitors. Each output channel is powered directly from its own isolated rail.

How is CMTI tested and what does >100kV/µs mean in practice?

CMTI is measured per DIN EN IEC 60747-17 using 1500V common-mode step with ≥100kV/µs slew rate. In practice, this rating ensures the driver remains immune to false triggering during rapid voltage transients across isolation barriers - critical when switching 1200V SiC devices at 50kV/µs in motor drives.

Is the SOIC-16 WB package RoHS and halogen-free compliant?

Yes. MP18831-A4CGSE-P meets RoHS Directive 2011/65/EU and is halogen-free per IEC 61249-2-21. It carries CQC certification per GB 4943.1-2011 and is rated for 5000m altitude operation with reinforced insulation classification in SOIC-16 WB.

What thermal derating applies above 25°C ambient?

For SOIC-16 WB, safety-limiting power drops linearly from 2215mW at 25°C to zero at 150°C (θ_JA = 56°C/W). At 85°C ambient, maximum safe dissipation is ~1500mW per channel - verified via thermal derating curves in datasheet Figure 14.