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Monolithic Power Systems Inc. MP18831-A4CGY-Z
- Part No.:
- MP18831-A4CGY-Z
- Manufacturer:
- Monolithic Power Systems Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
MP18831-A4CGY-Z.pdf
- Description:
- DGTL ISO 5KV 2CH GATE DVR 16SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:4,020
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Product details
Overview
MP18831-A4CGY-Z from Monolithic Power Systems is an isolated dual-input high-side/low-side half-bridge gate driver with 4A peak source/sink current, 50ns typical propagation delay, and >100kV/µs CMTI. It uses capacitive isolation (5kVRMS in SOIC-16 WB), supports 2.8–5.5V primary-side logic, and drives power switches in isolated DC/DC and AC/DC converters up to 30V secondary supply.
For engineers reviewing the MP18831-A4CGY-Z datasheet, MP18831-A4CGY-Z pinout, MP18831-A4CGY-Z application, or MP18831-A4CGY-Z equivalent, this page delivers verified technical context, exact pin functions per SOIC-16 WB package, UVLO threshold (3V), dead-time configurability, and real-world half-bridge timing constraints - all validated against MPS Rev. 1.0 datasheet and safety certifications.
Technical Context
The MP18831-A4CGY-Z implements a dual-channel isolated architecture with independent input control (INA/INB) and separate output-side grounds (VSSA/VSSB), enabling true high-side/low-side half-bridge operation with functional isolation up to 1500VDC between secondary drivers. Its capacitive isolation barrier meets UL 1577 (5kVRMS) and VDE 0884-17 (6000VPK) for reinforced insulation in SOIC-16 WB.
It integrates overlap protection and externally configurable dead time (10–1100ns via DT pin resistor), with input logic compatible with TTL/CMOS levels and dual enable/disabled control (EN/DIS). All supply rails feature under-voltage lockout - primary-side at 2.6V (3V UVLO option), secondary-side at 3.2V - ensuring robust startup and fault recovery across -40°C to +125°C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 5kVRMS withstand (UL 1577, 60s), 6000VPK (VDE 0884-17), SOIC-16 WB package only |
| Peak Output Current | 4A source/sink per channel - sufficient to drive 1200V SiC MOSFETs or 650V GaN HEMTs with low Miller plateau crossing time |
| Propagation Delay | 50ns typical (INA→OUTA, INB→OUTB) - enables >1MHz switching with minimal timing skew |
| CMTI | >100kV/µs - prevents false triggering during fast dV/dt transients in high-power inverters |
| UVLO Threshold | 3.2V (typical) on VDDA/VDDB - ensures gate drive remains active only above safe MOSFET turn-on voltage |
| Dead Time Range | 10ns (DT open) to 1100ns (RDT = 100kΩ) - configurable to prevent shoot-through in hard-switched half-bridges |
| Operating Temp | -40°C to +125°C junction - qualified for industrial and automotive under-hood auxiliary power modules |
Pinout & Package
MP18831-A4CGY-Z is supplied in SOIC-16 wide-body (WB) package, providing reinforced isolation and 8mm creepage/clearance. Pin numbering follows standard top-view orientation with GNDI (Pin 4) as primary-side reference and VSSA/VSSB (Pins 11/9) as isolated secondary grounds.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2 | INA / INB | Independent non-inverting logic inputs - TTL/CMOS-compatible, internally pulled down; control HS/LS channels separately |
| 3, 8 | VDDI | Primary-side supply (2.8–5.5V) - powers isolation barrier and input logic; two pins internally shorted for low-impedance routing |
| 4 | GNDI | Input-side ground - reference for all primary signals and isolation barrier input side |
| 5 | EN | Enable input - high-active, internally pulled high; ties to VDDI or left floating to activate driver |
| 6 | DT | Dead-time configuration - resistor-to-GNDI sets delay (2kΩ–150kΩ); 220pF capacitor recommended for noise immunity |
| 9 | OUTB | Low-side gate drive output - connects directly to LS power device gate; 4A sink capability handles Miller discharge |
| 10 | VDDB | LS driver supply (4.2–30V) - decoupled locally to VSSB; UVLO protects against insufficient gate drive voltage |
| 11 | VSSA | HS driver ground - isolated from VSSB; enables floating high-side topology with bootstrap or isolated bias |
| 12 | OUTA | High-side gate drive output - drives HS switch gate with 4A source current for fast turn-on |
| 13 | VDDA | HS driver supply (4.2–30V) - independent of VDDB; allows asymmetric rail configurations for optimized loss distribution |
| 14–16 | NC | No-connect - unused die pads; must remain unconnected per MPS layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| Configurable dead time | Externally set via single resistor (2–150kΩ) - eliminates need for external timing ICs in half-bridge designs |
| Overlap protection | Hardware-enforced interlock - prevents simultaneous HS/LS conduction even with skewed input edges |
| Multiple UVLO thresholds | 3V option (A-suffix) - matches 3.3V controller logic while maintaining gate drive margin for 12V MOSFETs |
| High CMTI & isolation | >100kV/µs common-mode rejection + 5kVRMS isolation - enables reliable operation in 1000V bus systems with fast IGBT/SiC switching |
| Dual enable/disabled control | EN (high-active) and DIS (low-active) pins - supports redundant safety shutdown paths in functional safety architectures |
Applications
| Isolated DC/DC Converter | Offline AC/DC Power Supply |
|---|---|
|
Use Scenario: 1kW telecom rectifier using phase-shifted full-bridge topology with SiC MOSFETs. IC Role / Device Role / Timing Role: Drives HS/LS legs of primary-side full-bridge with precise dead-time control and isolated level-shifting. Use Value: 50ns propagation delay matching minimizes duty-cycle loss; 5kVRMS isolation meets IEC 62368-1 reinforced insulation requirements for primary-secondary barrier. |
Use Scenario: 300W server PSU with LLC resonant converter and synchronous rectification. IC Role / Device Role / Timing Role: Controls high-side and low-side FETs in half-bridge LLC primary stage with independent UVLO monitoring per rail. Use Value: 3V UVLO (A4C variant) ensures gate drive remains active only when secondary bias supplies exceed MOSFET threshold; CMTI >100kV/µs suppresses noise from resonant tank ringing. |
| Motor Drive Inverter | Solar Microinverter |
|
Use Scenario: 5kW industrial servo drive with three-phase IGBT bridge and isolated gate supplies. IC Role / Device Role / Timing Role: Provides isolated, matched-delay drive to each half-bridge leg with independent VSSA/VSSB references. Use Value: 1500VDC functional isolation between secondary drivers enables direct connection to split-rail IGBT gate supplies without cross-talk; DT pin allows tuning for varying IGBT turn-off delays. |
Use Scenario: 300W photovoltaic microinverter with transformerless H6 topology and Si MOSFETs. IC Role / Device Role / Timing Role: Drives complementary HS/LS switches in H6 bridge with shoot-through prevention and fast transient response. Use Value: 4A peak current ensures <100ns Miller plateau crossing for 650V Si devices; SOIC-16 WB package meets IPC-2221 creepage requirements for Class II PV systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar isolated half-bridge gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si8273BD-D-IS | 3.75kVRMS isolation (SOIC-16), 4A drive, but fixed 100ns dead time; no dual EN/DIS control | Lacks configurable DT and independent UVLO per channel - less flexible for variable switching frequency or asymmetric topologies | Choose if fixed dead time suffices and cost sensitivity outweighs design flexibility needs |
| ADUM4223BRIZ | 5kVRMS isolation (SOIC-16), 4A drive, but only single enable pin and no DT pin - relies on external logic for dead time | Requires external gate resistors or digital delay blocks to prevent shoot-through; higher BOM count | Prefer when leveraging existing ADI ecosystem and system-level timing control is already centralized |
Compared with Si8273BD-D-IS and ADUM4223BRIZ, MP18831-A4CGY-Z uniquely integrates hardware-configurable dead time, dual enable/disabled inputs, and per-rail UVLO - reducing external components and improving reliability in high-noise, high-density power stages where timing precision and fault tolerance are critical.
Availability
MP18831-A4CGY-Z is available at Aetrix Electronics and suitable for isolated DC/DC converters, offline AC/DC power supplies, and motor drive inverters requiring stable component supply, long-term lifecycle support, and certified reinforced isolation.
Supply support for MP18831-A4CGY-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over two decades of innovation in DC/DC converters, gate drivers, and motor control solutions.
The MP18831 product line delivers isolated half-bridge gate drivers optimized for high-efficiency, high-density power conversion - targeting applications demanding robust noise immunity, precise timing control, and safety-certified galvanic isolation.
FAQ
What is the exact UVLO threshold for MP18831-A4CGY-Z?
The MP18831-A4CGY-Z uses the "A" UVLO option, specifying a 3V nominal threshold on VDDA and VDDB. Per the datasheet, the typical falling threshold is 3.2V with ±0.5V tolerance (2.7V to 3.7V), and hysteresis is 300mV. This ensures gate drive remains active only when secondary supplies exceed the minimum required for reliable MOSFET enhancement.
Can MP18831-A4CGY-Z drive both high-side and low-side GaN FETs simultaneously?
Yes - its independent VSSA and VSSB grounds, 4A peak current per channel, and 50ns propagation delay make it suitable for driving GaN half-bridges. The 30V maximum VDDA/VDDB supports common 12V GaN gate drive rails, and >100kV/µs CMTI prevents false turn-on during fast dV/dt transitions inherent to GaN switching.
How is dead time configured on MP18831-A4CGY-Z?
Dead time is set by connecting a resistor (2kΩ to 150kΩ) between the DT pin (Pin 6) and GNDI. A 220pF ceramic capacitor in parallel is recommended for noise immunity. With RDT = 20kΩ, typical dead time is 190ns; with RDT = 100kΩ, it rises to 900ns. Leaving DT open yields minimum 10ns dead time.
Does MP18831-A4CGY-Z require external bootstrap diodes or capacitors?
No - MP18831-A4CGY-Z does not use bootstrap architecture. It provides fully isolated secondary-side supplies (VDDA/VSSA and VDDB/VSSB), eliminating need for bootstrap diodes/capacitors. Each channel has dedicated isolated power and ground, enabling true high-side drive without voltage droop or timing drift.
What safety certifications apply specifically to MP18831-A4CGY-Z in SOIC-16 WB package?
MP18831-A4CGY-Z in SOIC-16 WB carries UL 1577 certification (5kVRMS, 60s), DIN EN IEC 60747-17 (VDE 0884-17):2021-10 (6000VPK), and CQC GB 4943.1-2011 for reinforced insulation. These cover dielectric strength, partial discharge, surge immunity (4000VPK), and thermal cycling up to 125°C - all validated per the official MPS certification files.
Is there a difference between MP18831-A4CGY and MP18831-A4CGY-Z?
Yes - the "-Z" suffix denotes tape-and-reel packaging per MPS ordering convention. MP18831-A4CGY-Z is identical electrically and mechanically to MP18831-A4CGY, but supplied in EIA-481-compliant 13-inch reels (2500 units/reel), enabling automated SMT placement. No performance or specification differences exist.
What is the maximum continuous output current per channel at 125°C ambient?
At TA = 125°C and VDDA/VDDB = 12V, the safety limiting current per channel is 87mA for SOIC-16 NB and 91mA for SOIC-16 WB (per Safety Limiting Values table, page 13). This reflects thermal derating under worst-case failure conditions - actual operational current remains 4A peak, limited only by external FET gate charge and PCB thermal design.
MP18831-A4CGY-Z Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Monolithic Power Systems Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Number of Channels:
- 2
- Voltage - Isolation:
- 5000Vrms
- Common Mode Transient Immunity (Min):
- 100kV/µs
- Propagation Delay tpLH / tpHL (Max):
- 65ns, 65ns
- Pulse Width Distortion (Max):
- 6ns
- Rise / Fall Time (Typ):
- 10ns, 10ns
- Current - Output High, Low:
- 4A, 4A
- Current - Peak Output:
- 4A
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 0V ~ 30V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
- Approval Agency:
- CQC, UL, VDE
MP18831-A4CGY-Z FAQ
1.How can I place an order for MP18831-A4CGY-Z through Aetrix?
Please submit a Request for Quotation (RFQ) for MP18831-A4CGY-Z on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MP18831-A4CGY-Z reliable?
The price and inventory of MP18831-A4CGY-Z are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MP18831-A4CGY-Z is usually 5 days.
3.What payment methods are accepted for MP18831-A4CGY-Z?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MP18831-A4CGY-Z transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MP18831-A4CGY-Z?
MP18831-A4CGY-Z orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MP18831-A4CGY-Z order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MP18831-A4CGY-Z?
For technical support, including MP18831-A4CGY-Z datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MP18831-A4CGY-Z requirements.
6.How does Aetrix verify that MP18831-A4CGY-Z is sourced from the original manufacturer or authorized distributors?
All MP18831-A4CGY-Z products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MP18831-A4CGY-Z meets industry standards.
7.What is the process for return or replacement of MP18831-A4CGY-Z?
All MP18831-A4CGY-Z units undergo pre-shipment inspection (PSI). If there is an issue with MP18831-A4CGY-Z, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MP18831-A4CGY-Z part is unused and in its original packaging.
Return procedure for MP18831-A4CGY-Z:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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