Monolithic Power Systems Inc. MP18851-A4BGLU-P

Overview

MP18851-A4BGLU-P from Monolithic Power Systems is an isolated, dual-input, independent dual-channel gate driver IC with 4A peak source/sink current per channel, 50ns typical propagation delay, and >100kV/µs common-mode transient immunity (CMTI). It drives high-side and low-side power switches in isolated half-bridge topologies using capacitive isolation, supporting up to 30V secondary-side supply and operating across –40°C to +125°C for offline AC/DC and isolated DC/DC converters.

For engineers reviewing the MP18851-A4BGLU-P datasheet, MP18851-A4BGLU-P pinout, MP18851-A4BGLU-P application, or MP18851-A4BGLU-P equivalent, this part delivers functional isolation between output channels (700VDC for LGA-13), UVLO-selectable thresholds (5V option), and SOIC-16 WB/LGA-13 package variants certified to UL 1577 (2.5kVRMS) and VDE 0884-17 (3535VPK).

Technical Context

The MP18851-A4BGLU-P implements MPS's proprietary capacitive isolation barrier separating primary-side logic control (INA/INB/EN/DIS) from two fully independent secondary-side gate drivers. Each output channel features separate VDDA/VSSA and VDDB/VSSB supplies, enabling asymmetric rail configurations and true galvanic separation between high-side and low-side switch grounds.

It supports dual-driver mode (INA→OUTA, INB→OUTB) with no internal overlap logic, allowing external dead-time control. Input-side operation spans 2.8V–5.5V (TTL/CMOS compatible), while secondary-side UVLO is fixed at 5V (–A4B variant), with shutdown initiated by pulling DIS high or EN low.

Key Specifications

Pinout & Package

LGA-13 (5mm × 5mm) package with exposed thermal pad; RoHS-compliant, halogen-free, MSL Level 3 per JEDEC J-STD-020.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel isolated gate driver applications.

Compared with Si823H4BB-IS and UCC5390SCD, MP18851-A4BGLU-P uniquely combines LGA-13 compactness, dual independent enable/disable controls (EN/DIS), and guaranteed >100kV/µs CMTI - making it optimal for space-constrained, high-reliability SiC inverter designs requiring fast, asymmetric fault response.

Availability

MP18851-A4BGLU-P is available at Aetrix Electronics and suitable for isolated DC/DC converters, offline AC/DC power supplies, and motor drive inverters requiring stable component supply across extended temperature and high-CMTI operational demands.

Supply support for MP18851-A4BGLU-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, including DC/DC converters, LED drivers, and isolated gate drivers for industrial, computing, and automotive markets.

The MP18851 product line delivers integrated, capacitive-isolated dual-channel gate drivers targeting high-efficiency, high-density power conversion systems where timing precision, noise immunity, and package miniaturization are critical.

FAQ

What does the "A4B" suffix indicate in MP18851-A4BGLU-P?

The "A4B" denotes the UVLO threshold configuration: "A" specifies active-low disable (DIS) control logic, "4" indicates 4A peak output current per channel, and "B" selects the 5V output-side UVLO threshold (VDDA_UVLO = 5.0V, ±0.5V). This matches the –A4B variant in the MP18851 selection guide.

Can MP18851-A4BGLU-P drive both high-side and low-side switches in a half-bridge with independent ground references?

Yes. The device provides fully independent secondary-side supplies (VDDA/VSSA and VDDB/VSSB), allowing each output channel to reference separate ground potentials. This enables true high-side/low-side operation in floating half-bridge configurations without shared ground constraints or bootstrap limitations.

Does the LGA-13 package meet reinforced insulation requirements per IEC 62368-1?

No. Per MPS safety documentation, the LGA-13 variant provides basic insulation only (700VDC functional isolation, 2.5kVRMS withstand), with maximum working voltage rated at 480VDC. Reinforced insulation is specified only for the SOIC-16 WB package (5kVRMS, 6000VPK).

How is propagation delay matching maintained between channels?

Channel-to-channel propagation delay matching (tPDM) is guaranteed ≤6ns over temperature (–40°C to +125°C) and supply variations. This is achieved through matched internal circuitry and capacitive isolation structure - critical for minimizing shoot-through in synchronous rectifier and ZVS topologies.

What is the recommended PCB layout practice for the thermal pad on the LGA-13 package?

The exposed thermal pad (pin 13) must be soldered to a minimum 100mm² copper pour connected to VSSA/VSSB. Use ≥4 thermal vias (0.3mm diameter, spaced ≤1mm apart) to inner ground planes. Avoid routing signal traces beneath the pad to preserve isolation integrity and thermal performance.

Is the DIS pin compatible with open-drain microcontroller GPIOs?

Yes. The DIS pin has an internal 200kΩ pull-down resistor and accepts standard CMOS logic levels. An open-drain GPIO pulled to VDDI (via external 10kΩ) can directly drive DIS - asserting high disables both outputs within 50ns (tPDDIS), meeting fast-fault response requirements.

Does MP18851-A4BGLU-P support 100% duty cycle operation on the high-side output?

Yes. Unlike bootstrap-based drivers, the isolated secondary-side supply (VDDA/VSSA) eliminates duty-cycle limitations. OUTA can remain continuously high as long as VDDA remains above UVLO, enabling direct drive of high-side switches in synchronous buck or active-clamp topologies.