Monolithic Power Systems Inc. MP20045DQ-33-LF-Z
- Part No.:
- MP20045DQ-33-LF-Z
- Manufacturer:
- Monolithic Power Systems Inc.
- Package:
- 8-VDFN Exposed Pad
- Datasheet:
-
MP20045DQ-33-LF-Z.pdf
- Description:
- IC REG LINEAR 3.3V 1A 8QFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,488
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MP20045DQ-33-LF-Z from Monolithic Power Systems is a low-noise, 1A adjustable-output linear regulator with 140mV dropout at full load, 110μA ground current, and 13μVRMS output noise. It operates from 2.5V to 5.5V input and delivers stable 3.3V output (via external resistor divider), targeting power-sensitive portable electronics requiring high PSRR and precise voltage regulation.
For engineers reviewing the MP20045DQ-33-LF-Z datasheet, MP20045DQ-33-LF-Z pinout, MP20045DQ-33-LF-Z application, or MP20045DQ-33-LF-Z equivalent, key selection criteria include dropout performance at 1A, thermal shutdown threshold (150°C), open-drain PG status signaling, EN logic thresholds (1.5V high / 0.4V low), and QFN8 package thermal resistance (θJA = 50°C/W).
Technical Context
The MP20045DQ-33-LF-Z employs an internal PMOS pass transistor enabling ultra-low dropout and minimal quiescent current. Its feedback architecture uses a fixed 1.5V reference at the FB pin, allowing precise output setting via external resistive dividers - for 3.3V output, R1 ≈ 12kΩ and R2 = 100kΩ per design equations.
It integrates protection features including foldback current limiting (1.4–3.0A in-regulation limit), thermal shutdown with 20°C hysteresis, and open-drain power-good monitoring that asserts low when VOUT drops below 80–86% of nominal. The PG pin requires an external pull-up for proper logic-level interfacing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 1A continuous - supports high-current subsystems like RF transceivers or microcontroller cores without derating at TA ≤ 85°C. |
| Dropout Voltage | 140mV at 1A - enables operation with only 3.44V input for stable 3.3V output, critical for single-cell Li-ion or multi-rail battery systems. |
| Ground Current | 110μA at 100μA load - minimizes standby power loss in always-on circuits such as real-time clocks or sensor wake-up logic. |
| Output Noise | 13μVRMS (10Hz–100kHz) - meets stringent analog/RF supply requirements, e.g., ADC reference rails or PLL VCO supplies. |
| PSRR | 56dB at 1kHz - suppresses switching noise from upstream DC/DC converters, preserving signal integrity in mixed-signal SoCs. |
| Enable Threshold | EN high = 1.5V min, EN low = 0.4V max - compatible with 1.8V/3.3V GPIO control without level-shifting. |
| Power-Good Accuracy | PG trip at 80–86% VOUT with 6% hysteresis - provides reliable system reset sequencing and brown-out detection. |
Pinout & Package
The MP20045DQ-33-LF-Z is housed in an 8-pin QFN package (3mm × 3mm, exposed thermal pad), optimized for compact PCB layouts and efficient heat dissipation when the pad is soldered to a solid GND plane.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN (Pins 1, 2) | Input supply rail | Accepts 2.5–5.5V; must be bypassed with ≥2.2μF ceramic capacitor; pins are internally connected but require external tie-together for optimal current sharing. |
| VOUT (Pins 3, 4) | Regulated output node | Delivers 3.3V (set via FB divider); requires ≥2.2μF low-ESR ceramic cap to GND; pins must be externally shorted for full 1A capability. |
| FB (Pin 5) | Feedback input | Monitors output via resistor divider; 1.5V internal reference sets VOUT = 1.5V × (1 + R1/R2); for 3.3V, R2 = 100kΩ, R1 ≈ 12kΩ. |
| GND (Pin 6) | Ground reference & thermal path | Exposed pad must be soldered to PCB GND plane to achieve θJA = 50°C/W and prevent thermal shutdown under load. |
| PG (Pin 7) | Open-drain power-good flag | Asserts low when VOUT falls below 80–86% of target; requires external pull-up (e.g., 10kΩ to 3.3V) for MCU reset or sequencing logic. |
| EN (Pin 8) | Enable control input | Active-high logic: >1.5V enables regulator; <0.4V disables output and reduces supply current to 5–16μA; must never float. |
Key Features
| Feature | Design Value |
|---|---|
| Low-noise regulation | 13μVRMS output noise enables clean power for precision analog circuits and RF front-ends without additional filtering. |
| High PSRR at audio frequencies | 56dB rejection at 1kHz allows co-location with noisy digital ICs while maintaining signal fidelity in audio codecs or sensors. |
| Thermal protection with hysteresis | 150°C shutdown with 20°C recovery gap prevents cycling during sustained overload, ensuring safe fault handling in sealed enclosures. |
| Adjustable output with precision reference | 1.5V ±2.5% FB reference enables accurate 3.3V (±2.5%) output across temperature and line/load variations. |
| Ultra-low quiescent current | 110μA ground current at light load extends battery life in IoT endpoints where sleep-mode current dominates runtime. |
Applications
| Wireless LAN Modules | Industrial Handheld Scanners |
|---|---|
Use Scenario: Powering 2.4GHz/5GHz Wi-Fi SoC RF sections and baseband processors in compact access points or client adapters. IC Role / Device Role / Timing Role: Low-noise 3.3V LDO supplying VDD_IO and VDDA rails for WLAN transceivers and ADCs. Use Value: 13μVRMS noise and 56dB PSRR prevent EVM degradation and maintain -45dB error vector magnitude in 802.11ac transmission. | Use Scenario: Regulating main system voltage in ruggedized barcode scanners used in warehouse logistics. IC Role / Device Role / Timing Role: Primary 3.3V supply for ARM Cortex-M7 MCU, CMOS image sensor, and laser driver circuitry. Use Value: 140mV dropout ensures operation down to 3.44V input from partially discharged Li-ion packs, extending field usage time by >18%. |
| Medical Patient Monitors | Automotive Infotainment Displays |
Use Scenario: Providing clean 3.3V bias to ECG front-end amplifiers and SAR ADCs in portable diagnostic devices. IC Role / Device Role / Timing Role: Precision analog supply rail decoupled from noisy digital domains using PG-monitored sequencing. Use Value: Sub-15μV RMS noise floor preserves 16-bit effective resolution in biopotential measurements without post-processing correction. | Use Scenario: Powering display interface logic (LVDS transmitter, touch controller) in automotive center-stack displays. IC Role / Device Role / Timing Role: Secondary LDO generating 3.3V from 5V domain, synchronized via EN to display power-up sequence. Use Value: Open-drain PG output enables fail-safe backlight enable timing, preventing visible flash during cold cranking (9V battery dip). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar low-noise, 1A LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6210B332MR-G | Fixed 3.3V output (no FB pin); 250mV dropout at 1A; 25μA IQ; no PG output. | Lacks adjustability and power-good signaling - suitable only for simple point-of-load use with no sequencing needs. | Select when board space is constrained and 3.3V is immutable; avoid if system requires dynamic voltage scaling or reset coordination. |
| Analog Devices ADM7172ACPZ-3.3-R7 | Fixed 3.3V; 175mV dropout at 1A; 250μA IQ; 7μVRMS noise; integrated soft-start. | Higher noise margin but includes soft-start - beneficial for avoiding inrush into large capacitive loads, yet consumes more quiescent power. | Prefer for applications needing controlled ramp-up (e.g., FPGA core rails), but not for battery-critical designs due to 2.3× higher ground current. |
Compared with XC6210B332MR-G and ADM7172ACPZ-3.3-R7, the MP20045DQ-33-LF-Z uniquely balances ultra-low dropout (140mV), sub-15μV noise, and full system visibility via PG/EN - making it optimal for portable, battery-powered systems demanding both efficiency and robust power management.
Availability
MP20045DQ-33-LF-Z is available at Aetrix Electronics and suitable for notebook computers, handheld medical instruments, wireless communication modules, and industrial portable scanners requiring stable component supply with RoHS-compliant, lead-free packaging.
Supply support for MP20045DQ-33-LF-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.
The MP20045 belongs to MPS's low-noise LDO product line, engineered specifically for battery-powered portable electronics where ultra-low dropout, minimal quiescent current, and high PSRR are essential for extending runtime and preserving signal integrity.
FAQ
What is the minimum input voltage required to maintain 3.3V output at 1A load?
The MP20045DQ-33-LF-Z requires VIN ≥ 3.44V to sustain 3.3V output at 1A, based on its 140mV dropout specification. Below this, output voltage collapses linearly; operation down to 2.5V input is supported only at reduced load currents per the dropout vs. IOUT curve.
Can the MP20045DQ-33-LF-Z be used without the FB resistor divider?
No - the "DQ" suffix denotes the adjustable version, which requires an external resistor divider from VOUT to FB to set the output voltage. For 3.3V, typical values are R2 = 100kΩ and R1 = 12kΩ. Fixed-output variants (e.g., MP20045DQ-33) omit FB connection.
How should the exposed thermal pad on the QFN8 package be connected?
The exposed pad (Pin 6) must be soldered to a dedicated PCB copper pour tied directly to the system GND plane. At least 4 thermal vias (0.3mm diameter) connecting the pad to inner-layer GND planes are recommended to achieve θJA = 50°C/W and prevent thermal shutdown at full load.
Does the PG pin require an external pull-up resistor?
Yes - PG is open-drain and must be pulled up to a valid logic-high voltage (e.g., 3.3V or VOUT) via a 10kΩ resistor. Without pull-up, PG remains floating and cannot signal power-good status to host controllers or sequencers.
What is the maximum allowable power dissipation in the QFN8 package at 25°C ambient?
At TA = 25°C, the QFN8 package supports up to 2.0W continuous power dissipation before thermal shutdown activates, calculated as PD(MAX) = (TJ(MAX) − TA)/θJA = (125°C − 25°C)/50°C/W = 2.0W. Derate linearly above 25°C ambient.
Is the MP20045DQ-33-LF-Z compatible with ceramic output capacitors?
Yes - it is optimized for 2.2μF X5R/X7R ceramic capacitors with ESR < 0.9Ω. Larger values (e.g., 4.7μF) improve transient response but may affect stability if ESR falls outside the 0.1–0.9Ω window shown in Figure 2 of the datasheet.
What happens during thermal shutdown, and how does recovery work?
When junction temperature exceeds 150°C, the PMOS pass device turns off completely. Output drops to zero. After cooling by 20°C (to ~130°C), the device automatically resumes regulation. This hysteresis prevents oscillatory on/off cycling during sustained overload conditions.
MP20045DQ-33-LF-Z Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Monolithic Power Systems Inc.
- Series:
- -
- Package/Case:
- 8-VDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 3.3V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.28V @ 1A
- Current - Output:
- 1A
- Current - Quiescent (Iq):
- 110 µA
- Current - Supply (Max):
- -
- PSRR:
- 56dB (1kHz)
- Control Features:
- Enable, Power Good
- Protection Features:
- Over Current, Over Temperature
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-QFN (3x3)
MP20045DQ-33-LF-Z FAQ
1.How can I place an order for MP20045DQ-33-LF-Z through Aetrix?
Please submit a Request for Quotation (RFQ) for MP20045DQ-33-LF-Z on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MP20045DQ-33-LF-Z reliable?
The price and inventory of MP20045DQ-33-LF-Z are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MP20045DQ-33-LF-Z is usually 5 days.
3.What payment methods are accepted for MP20045DQ-33-LF-Z?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MP20045DQ-33-LF-Z transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MP20045DQ-33-LF-Z?
MP20045DQ-33-LF-Z orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MP20045DQ-33-LF-Z order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MP20045DQ-33-LF-Z?
For technical support, including MP20045DQ-33-LF-Z datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MP20045DQ-33-LF-Z requirements.
6.How does Aetrix verify that MP20045DQ-33-LF-Z is sourced from the original manufacturer or authorized distributors?
All MP20045DQ-33-LF-Z products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MP20045DQ-33-LF-Z meets industry standards.
7.What is the process for return or replacement of MP20045DQ-33-LF-Z?
All MP20045DQ-33-LF-Z units undergo pre-shipment inspection (PSI). If there is an issue with MP20045DQ-33-LF-Z, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MP20045DQ-33-LF-Z part is unused and in its original packaging.
Return procedure for MP20045DQ-33-LF-Z:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MP20045DQ-33-LF-Z Tags

-
MIC5504-1.8YM5-TR
Microchip Technology

-
MIC5504-3.3YM5-TR
Microchip Technology

-
MIC5365-3.0YC5-TR
Microchip Technology

-
MIC5365-1.8YC5-TR
Microchip Technology

-
MIC5365-2.5YC5-TR
Microchip Technology

-
MIC5365-3.3YC5-TR
Microchip Technology

-
MIC5365-3.3YD5-TR
Microchip Technology

-
MIC5317-3.3YM5-TR
Microchip Technology

-
TLV1117LV33DCYR
Texas Instruments

-
MIC5317-3.3YMT-TZ
Microchip Technology

-
MIC5528-3.3YMT-TR
Microchip Technology

-
TLV75801PDRVR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

