Monolithic Power Systems Inc. MP2667GG-0000-Z

Overview

MP2667GG-0000-Z from Monolithic Power Systems is a single-cell Li-ion/Li-polymer linear battery charger with integrated power path management, I²C programmability, and dual FET architecture (300 mΩ IN→SYS LDO + 100 mΩ BATT→SYS switch). It delivers up to 1000 mA charge current, supports 4.35–5.5 V USB input, regulates system voltage to 5.00 V ±150 mV, and enables simultaneous system powering and battery charging in space-constrained wearables.

For engineers reviewing the MP2667GG-0000-Z datasheet, MP2667GG-0000-Z pinout, MP2667GG-0000-Z application, or MP2667GG-0000-Z equivalent, key selection considerations include I²C-configurable charge parameters (VBATT_REG: 3.60–4.545 V, ICC: 26–1049 mA), thermal regulation at 120°C, programmable input current limit (77–993 mA), and battery UVLO threshold (2.4–3.1 V).

Technical Context

The MP2667 implements a direct power path architecture with independent control of the IN→SYS LDO FET and BATT→SYS discharge FET, enabling true system priority startup even with deeply discharged batteries. Its charge algorithm executes three phases-pre-charge (programmable 6–25 mA), constant-current fast charge (26–1049 mA), and constant-voltage regulation (±0.5% accuracy at 4.200 V)-with auto-recharge triggered at 140–370 mV below full charge.

Power path operation is governed by real-time loop arbitration: when input current or voltage falls below programmed thresholds (VIN_MIN: 3.88–5.08 V; IIN_LIM: 77–993 mA), the IC reduces charge current or engages the battery FET to supplement system load. Fault handling includes NTC-based temperature monitoring (cold/hot thresholds set as % of VIN), input OVP (6.00 V), and system short-circuit protection limiting ISYS to 1.6 A.

Key Specifications

Pinout & Package

MP2667GG-0000-Z is housed in a 10-pin QFN package (2 mm × 2 mm, 0.5 mm pitch) with exposed thermal pad. The package supports high-density layout and efficient heat dissipation in ultra-thin portable designs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar single-cell Li-ion charger with power path applications.

Compared with BQ24296RGER and MAX77818EWJ+T, MP2667GG-0000-Z uniquely balances ultra-compact size, full I²C configurability (including NTC and UVLO), and linear simplicity-making it optimal for sub-10 mm-thick wearables where board area and analog integrity outweigh raw efficiency gains.

Availability

MP2667GG-0000-Z is available at Aetrix Electronics and suitable for wearable fitness trackers, smart Bluetooth headphones, ultra-thin smartwatches, and wireless sensor nodes requiring stable component supply across design-in, prototyping, and volume production phases.

Supply support for MP2667GG-0000-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over two decades of expertise in DC/DC converters, battery chargers, and motor drivers.

The MP2667 belongs to MPS's highly integrated linear battery charger product line, designed specifically for space-constrained portable electronics requiring robust power path management, I²C configurability, and comprehensive battery protection.

FAQ

What is the maximum allowable input voltage for MP2667GG-0000-Z, and what protection activates beyond that?

The absolute maximum input voltage is +13 V, but the device enters over-voltage protection (OVP) at 6.00 V (typical rising threshold). At this point, the IN→SYS LDO FET turns off immediately to protect internal circuitry. Recovery occurs only after input voltage drops below 5.633 V (6.00 V − 367 mV hysteresis), ensuring stable re-engagement without oscillation.

How does the MP2667 handle system power when the battery is deeply discharged or missing?

The MP2667 prioritizes system startup using its IN→SYS LDO FET. Even with a 0 V battery, the IC powers the SYS rail from the input source (4.35–5.5 V) and regulates it to 5.00 V ±150 mV. This ensures immediate MCU/peripheral operation without waiting for battery pre-charge, a critical feature for wearables requiring instant-on functionality.

Can the battery UVLO threshold be adjusted, and what is its functional range?

Yes, the battery under-voltage lockout (UVLO) threshold is fully programmable via I²C register REG04[1:0], spanning 2.4 V to 3.1 V in 0.1 V steps. At default setting (2.8 V), the hysteresis is 227 mV-meaning the FET reconnects only when battery voltage rises above 3.027 V, preventing oscillation near cutoff.

What is the role of the INT pin beyond interrupt signaling?

INT serves dual functions: (1) open-drain interrupt output for charge status/fault reporting (e.g., EOC, thermal fault), and (2) hardware-controlled battery disconnect. Pulling INT low for >8 seconds forces the BATT→SYS FET off, reducing system quiescent current to ≤5 μA-enabling true shipping mode for factory packaging and long-term storage.

Does MP2667GG-0000-Z support charging from non-USB sources, and what are the limits?

Yes-it accepts any 4.35–5.5 V DC source, including wall adapters and power banks. The input over-voltage protection triggers at 6.00 V, and absolute maximum rating is 13 V. However, sustained operation above 5.5 V violates recommended conditions and may degrade reliability or trigger OVP repeatedly.

How is thermal regulation implemented, and is it user-configurable?

Thermal regulation is implemented via an on-die temperature sensor and programmable junction threshold. Register REG06[1:0] sets TJ_REG to 120°C (default), 125°C, 130°C, or disabled. When exceeded, the IC linearly reduces charge current to maintain die temperature at the setpoint-avoiding thermal shutdown and preserving system operation.

What is the minimum external capacitance required on the IN pin, and why is placement critical?

A minimum 1 μF ceramic capacitor is required between IN and GND, placed as close as possible to pins 1 and 5. This stabilizes the input rail during transient load changes (e.g., MCU wake-up bursts) and prevents false triggering of input UVLO due to localized voltage droop at the IC's input node.