Monolithic Power Systems Inc. MP28259DD-LF-Z

Overview

MP28259DD-LF-Z from Monolithic Power Systems is a fully integrated synchronous step-down DC/DC converter delivering 2A continuous output current with Constant-On-Time (COT) control, 4.2V–20V input range, and programmable switching frequency up to 1 MHz in a 2mm×3mm QFN12 package. It integrates high- and low-side MOSFETs (R_DS(ON) = 130 mΩ / 80 mΩ), supports adjustable output from 0.815V to 13V, and features power-good indication, soft-start, and comprehensive protection including OCP (latch-off mode), SCP, OVP, UVP, and thermal shutdown. It targets point-of-load regulation in compact networking and distributed power systems.

For engineers reviewing the MP28259DD-LF-Z datasheet, MP28259DD-LF-Z pinout, MP28259DD-LF-Z application, or MP28259DD-LF-Z equivalent, key selection criteria include its COT-based fast transient response, QFN12 footprint constraints, bootstrap capacitor requirement on BST pin, PG open-drain timing delay (0.5 ms + 0.5×SS), and OCP latch-off behavior versus hiccup-mode alternatives.

Technical Context

The MP28259DD-LF-Z employs Constant-On-Time (COT) control architecture with feed-forward input voltage dependence, enabling stable operation without external compensation while delivering sub-100 ns minimum off-time and 250 ns one-shot on-time at V_OUT = 1.2V. Its internal block includes dual MOSFET drivers with dead-time control, a 0.815V reference with ±12 mV tolerance over –40°C to +85°C, and a dedicated power-good comparator with 5% hysteresis.

Protection logic is tightly coupled to real-time current sensing: cycle-by-cycle OCP triggers after 50 μs hold-off if inductor current exceeds 3–4 A, while SCP activates when FB drops below 50% of V_REF under short-circuit conditions. UVLO has 3.1 V rising threshold with 300 mV hysteresis, and thermal shutdown engages at 150°C with 25°C hysteresis.

Key Specifications

Pinout & Package

MP28259DD-LF-Z is housed in a thermally enhanced 12-pin QFN package (2 mm × 3 mm, 0.5 mm pitch) with exposed thermal pad (Pin 2, 10, Exposed Pad). The package supports high-power density PCB layouts with multiple GND vias and wide SW trace routing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous step-down converter applications.

Compared with MP28259DD-A-LF-Z, the MP28259DD-LF-Z provides deterministic latch-off behavior ideal for safety-critical shutdown, while MPQ28259DD-LF-Z adds automotive qualification at no electrical trade-off-making it the sole choice for automotive applications but unnecessary for industrial or telecom use.

Availability

MP28259DD-LF-Z is available at Aetrix Electronics and suitable for networking equipment power rails, distributed point-of-load regulation, and industrial control I/O modules requiring stable component supply, RoHS-compliant packaging, and long-term production continuity.

Supply support for MP28259DD-LF-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP28259 belongs to MPS's high-efficiency, fast-transient synchronous buck converter product line, engineered for compact, high-density power delivery in networking, telecom, and industrial systems where rapid load response and minimal external components are critical.

FAQ

What is the recommended input capacitor configuration for MP28259DD-LF-Z?

Use a minimum 10 µF X5R/X7R ceramic capacitor placed directly at the IN pin with short, wide traces and multiple vias to GND. For systems with high input ripple current, add parallel bulk capacitance (e.g., 22–47 µF tantalum or polymer) to meet RMS current rating - calculated as I_CIN(RMS) ≈ I_OUT/2 at worst-case VIN = 2×VOUT. Ceramic dielectric stability ensures consistent performance across temperature.

How does the BST pin function, and what capacitor value is required?

The BST pin supplies the floating gate drive voltage for the high-side MOSFET via a bootstrap capacitor connected between BST and SW. A 0.1 µF X7R ceramic capacitor rated for ≥16 V is required; it charges through an internal diode when the low-side FET conducts. Layout must minimize loop inductance - place capacitor within 2 mm of BST/SW pins with direct copper pours and no vias in the path.

Can MP28259DD-LF-Z operate in forced PWM mode, or is skip mode unavoidable at light load?

MP28259DD-LF-Z automatically enters skip mode (pulse-frequency modulation) below critical load to maintain high efficiency; it does not support forced continuous conduction mode (CCM). Skip mode reduces switching losses but introduces higher output voltage ripple and potential jitter. For applications requiring constant frequency, external ramp compensation (R4/C4) and careful FB resistor selection are necessary to stabilize operation down to ~10 mA.

What is the exact behavior of the PG pin during startup and fault conditions?

The PG pin remains low (pulled to GND) until FB reaches 90% of the target output voltage, then transitions high after a fixed 0.5 ms delay plus half the soft-start time (total ~1 ms). During OVP, UVP, or thermal shutdown, PG goes low immediately. Under latch-off OCP, PG stays low until power is cycled - it does not assert high again until full restart sequence completes and regulation is re-established.

Is the exposed thermal pad electrically connected, and how should it be handled in PCB layout?

Yes, the exposed pad (Pins 2, 10, and Exposed Pad) is internally connected to GND and must be soldered to a solid GND copper pour with ≥4 thermal vias (0.3 mm diameter) to inner/ground layers. This connection is essential for thermal performance - omitting it degrades θ_JA from 70°C/W to >120°C/W and risks thermal shutdown at <1.5 A load. Avoid solder mask coverage on the pad surface.

How is output voltage accuracy affected by resistor divider selection and layout?

Output accuracy depends on FB reference tolerance (±12 mV), resistor ratio matching, and layout-induced leakage. Use 1% metal-film or thin-film resistors with R2 between 5 kΩ and 50 kΩ; place R1/R2 close to FB pin with guard ring around FB trace to minimize contamination leakage. Avoid routing near noisy signals - even 10 pA leakage into FB can cause >10 mV error at R2 = 100 kΩ.

Does MP28259DD-LF-Z support output capacitor ESR-based compensation, and when is external ramp needed?

Yes - MP28259DD-LF-Z supports both ESR-based and external ramp compensation. Use large-ESR capacitors (e.g., POSCAP, polymer) for inherent slope compensation in PWM mode. For low-ESR ceramic outputs, external ramp (R4/C4) is mandatory to prevent subharmonic oscillation; design must satisfy equation (5) for stability and equation (9) for jitter suppression, with R4/C4 values verified via bench testing under worst-case load transients.