Monolithic Power Systems Inc. MP28301GG-Z

Overview

MP28301GG-Z from Monolithic Power Systems is an integrated power management IC combining a 700mA step-down converter and a 100mA LDO in a single QFN-12 (2mm×2mm) package. It delivers ultra-low quiescent current (500nA buck / 300nA LDO), operates from 2.0V–5.5V input, supports seven selectable buck output voltages (0.8V–3.3V) and three LDO outputs (1.2V–3.0V), and targets battery-powered wearable and IoT systems requiring extended runtime at microamp loads.

For engineers reviewing the MP28301GG-Z datasheet, MP28301GG-Z pinout, MP28301GG-Z application, or MP28301GG-Z equivalent, this page provides verified technical context on its COT-controlled buck architecture, dual-regulator sequencing, PG indicator behavior, output discharge function, and thermal shutdown recovery-critical for low-power system power-up, brownout resilience, and battery voltage tracking.

Technical Context

The MP28301GG-Z implements a constant-on-time (COT) control scheme for its 700mA buck regulator, delivering ~1.5MHz switching frequency in CCM, 100% duty cycle operation near dropout, and fast transient response with minimal external capacitance. Its internal error amplifier tightens regulation while enabling seamless PWM-to-PFM transition during light-load operation.

The integrated 100mA LDO features independent 2.0V–5.5V input range, programmable output selection via CTRL4/CTRL5, 50mV dropout at 100mA, and over-temperature protection. Both regulators share separate enable/control logic (CTRL1–CTRL5), independent soft-start (110µs buck / 2ms LDO), and coordinated output discharge upon disable.

Key Specifications

Pinout & Package

MP28301GG-Z is housed in a thermally enhanced QFN-12 package (2mm × 2mm, 0.5mm pitch) with exposed thermal pad (EP) connected to GND for efficient heat dissipation in compact battery-powered layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output PMU applications.

Compared with TPS62748IRYTR, MP28301GG-Z offers superior voltage flexibility and fault robustness; versus MAX20004AATP+T, it eliminates BOM count and layout complexity by integrating both rails, despite higher IQ than TPS62748 but significantly lower than MAX20004.

Availability

MP28301GG-Z is available at Aetrix Electronics and suitable for wearable health monitors, smart sensor nodes, portable medical instruments, and industrial asset trackers requiring stable component supply across long-lifecycle battery-powered designs.

Supply support for MP28301GG-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP28301 belongs to MPS's ultra-low-IQ power management unit (PMU) product line, engineered specifically for energy-constrained edge devices where multi-year battery life, small form factor, and dual-rail integration are mandatory.

FAQ

What is the minimum input voltage required for the buck regulator to maintain regulation?

The MP28301GG-Z buck regulator maintains regulation down to 2.0V input, with UVLO rising threshold at 1.8V (±0.15V). Below 2.0V, it enters 100% duty cycle mode-output voltage becomes VOUT ≈ VIN − (IOUT × 0.5Ω)-and regulation is lost once VIN falls below VOUT + dropout margin.

Can the buck and LDO operate from different input sources?

Yes. VIN1 (buck) and VIN2 (LDO) are electrically isolated inputs with independent 2.0V–5.5V ranges. This allows VIN1 to connect to a primary battery while VIN2 taps a pre-regulated rail, enabling noise isolation and flexible power tree design without cross-coupling.

How does the output discharge function behave during shutdown?

When CTRL1–CTRL3 or CTRL4–CTRL5 are pulled low, internal 50Ω discharge switches activate between OUT1/OUT2 and GND, discharging 10µF caps in <10ms. Discharge stops automatically once voltage drops below 0.4V, preventing reverse current into GND.

Is the PG1 signal compatible with 1.8V logic systems?

Yes. PG1 is open-drain with <400Ω RDS(ON); when pulled up to 1.8V via 220kΩ resistor, it sinks ≥1mA at 0.4V low level-meeting standard 1.8V GPIO input thresholds. No level shifter is needed for direct MCU interface.

What happens during a buck short-circuit event?

The buck enters hiccup mode: it disables switching, discharges OUT1 via internal path, waits ~100ms, then attempts restart. If short persists, cycle repeats. Average power remains <5mW, preventing thermal damage while signaling fault via sustained PG1 low.

Does the LDO require external compensation components?

No. The LDO is fully internally compensated and stable with 1µF ceramic output capacitor. Adding larger capacitance (e.g., 10µF) improves PSRR at <1kHz but is not required for stability per datasheet validation.

How is thermal performance affected by PCB layout?

θJA is specified at 80°C/W on 4-layer JEDEC PCB. Omitting thermal vias under the EP pad increases θJA by >30°C/W. For 700mA continuous load, ≥6 thermal vias (0.3mm diameter, filled) to inner GND plane are required to maintain TJ <125°C at TA=85°C.