Monolithic Power Systems Inc. MP28310GC-P

Overview

MP28310GC-P from Monolithic Power Systems is a monolithic power management IC integrating a 300mA step-down converter and a 100mA LDO regulator in a single CSP-12 (1.2mm × 1.6mm) package. It delivers ultra-low 500nA buck IQ and 300nA LDO IQ, operates from 2V–5.5V input, supports 7 selectable buck output voltages (1.2V–3.3V) and 3 LDO outputs (1.8V–3.0V), and features constant-on-time control for fast transient response-enabling extended battery life in wearable sensors and IoT edge nodes.

For engineers reviewing the MP28310GC-P datasheet, MP28310GC-P pinout, MP28310GC-P application, or MP28310GC-P equivalent, key selection considerations include its dual-regulator architecture with independent CTRL-based voltage selection, 100% duty-cycle operation below VOUT, integrated OCP/OTP/UVLO protection, and PG open-drain indicator-critical for low-power always-on systems requiring precise rail sequencing and fault visibility.

Technical Context

The MP28310GC-P implements a dual-path power architecture: a COT-controlled synchronous buck converter with cycle-by-cycle over-current protection and hiccup-mode short-circuit recovery, plus an independent LDO with 50mV dropout at 100mA and 40dB PSRR at 10Hz. Both regulators share a common ground but feature separate VIN inputs (VIN1 for buck, VIN2 for LDO) and independent enable/control logic via five dedicated CTRL pins.

Its control loop integrates an error amplifier to correct VOUT drift, while soft-start timing is fixed at 0.5ms (buck) and 2ms (LDO). The PG1 pin provides open-drain power-good indication with 90% threshold and 10% hysteresis, and both rails support output discharge during shutdown to prevent residual charge interference.

Key Specifications

Pinout & Package

CSP-12 (1.2mm × 1.6mm) package with 0.5mm pitch, 12-ball configuration, MSL Level 1, and bottom-side thermal pad for enhanced thermal dissipation in space-constrained designs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output PMIC applications.

Compared with TPS62748IRYR and MAX20004AATP+T, the MP28310GC-P uniquely delivers ultra-low IQ across both rails, on-the-fly VOUT reconfiguration via CTRL pins, and minimal 1.2mm × 1.6mm footprint-making it optimal for space- and energy-constrained wearable and medical edge devices where dual-rail independence and µA-level standby are non-negotiable.

Availability

MP28310GC-P is available at Aetrix Electronics and suitable for wearable health sensors, IoT edge node controllers, portable medical instruments, and smart hearing aids requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for MP28310GC-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over 20 years of expertise in DC-DC conversion, battery management, and motor drive solutions.

The MP28310GC-P belongs to MPS's ultra-low-IQ PMIC product line, designed specifically for battery-powered edge devices demanding multi-rail power integrity, extended operating life, and minimal PCB real estate-targeting wearables, medical sensors, and ultra-portable instrumentation.

FAQ

What is the maximum allowable input voltage for MP28310GC-P?

The absolute maximum input voltage for both VIN1 and VIN2 is 6V. However, the recommended operating range is strictly 2.0V to 5.5V. Exceeding 6V risks permanent damage to internal MOSFETs and control circuitry, as confirmed by MPS Absolute Maximum Ratings table (page 4). Operation above 5.5V voids parametric guarantees including IQ, regulation accuracy, and thermal performance.

How does the MP28310GC-P handle short-circuit conditions on the buck output?

When the buck output is shorted to GND, cycle-by-cycle over-current protection triggers continuously. After 200µs of sustained triggering, the device enters hiccup mode: it disables the power stage, discharges OUT1 via internal discharge path, waits ~5ms, then attempts automatic recovery. This repeats until the short is removed and VOUT returns to ≥90% of regulation-preventing thermal runaway without external intervention.

Can the buck and LDO operate from different input sources?

Yes. VIN1 (buck input) and VIN2 (LDO input) are electrically isolated power domains. They may be supplied from separate batteries, different points on a shared rail, or even different chemistries (e.g., Li-ion for VIN1, coin cell for VIN2). Each has independent UVLO thresholds and shutdown behavior, enabling flexible power architecture partitioning in multi-battery systems.

What is the purpose of the PG1 pin, and how should it be interfaced?

PG1 is an open-drain power-good indicator that goes high-impedance when VOUT1 reaches ≥90% of its programmed value and pulls low during UVLO, OCP, thermal shutdown, or startup. It requires an external 100kΩ–500kΩ pull-up resistor-typically to VIN1 or a stable CTRL voltage-and drives microcontroller GPIOs for rail monitoring and fault logging without additional supervisor ICs.

Is output capacitor ESR critical for stability in MP28310GC-P designs?

No. The MP28310GC-P uses constant-on-time control with internal compensation, making it inherently stable with low-ESR ceramic capacitors (X5R/X7R). Unlike voltage-mode controllers, it does not require specific ESR for phase margin. A 10µF 0603 ceramic capacitor is sufficient for buck output; LDO output requires only 1µF due to lower bandwidth and built-in error amplifier compensation.

How does the 100% duty-cycle mode function, and when is it activated?

When VIN1 drops below the programmed VOUT1, the controller extends on-time until the high-side MOSFET remains continuously on (100% duty cycle). VOUT1 then equals VIN1 minus ILOAD × RDS(ON)HS (0.25Ω). This mode sustains regulation down to VIN1 ≈ VOUT1 + (ILOAD × 0.25Ω), extending usable battery voltage range beyond conventional buck limits-critical for deep-discharge operation.

What thermal derating applies to the CSP-12 package at elevated ambient temperatures?

With θJA = 95°C/W (JEDEC-standard 2-layer board), the junction temperature rise is TJ = TA + (PD × 95). At TA = 85°C and full 300mA load (assuming 0.5V dropout and 85% efficiency), PD ≈ 26mW → TJ ≈ 87.5°C-well below the 125°C max operating limit. Derating begins above TA = 100°C; full 300mA load is not recommended above TA = 110°C without forced airflow or copper thermal pads.