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Monolithic Power Systems Inc. MP2965GQK-0000-P
- Part No.:
- MP2965GQK-0000-P
- Manufacturer:
- Monolithic Power Systems Inc.
- Category:
- Special Purpose Regulators
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
MP2965GQK-0000-P.pdf
- Description:
- DUAL-LOOP, DIGITAL, MULTI-PHASE
- Quantity:
- Payment:
- Shipping:
Inventory:3,325
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Product details
Overview
MP2965GQK-0000-P from Monolithic Power Systems is a dual-loop, digital, multi-phase PWM controller designed for Intel VR13.HC/AVSBUS CPU core voltage regulation. It supports up to 7-phase operation on Rail 1 and 3-phase on Rail 2, delivers 3MHz switching frequency, integrates on-chip EEPROM for configuration storage, and enables real-time monitoring via PMBus/I²C interface - deployed in high-density server VRMs with MPS Intelli-Phase power stages.
For engineers reviewing the MP2965GQK-0000-P datasheet, MP2965GQK-0000-P pinout, MP2965GQK-0000-P application, or MP2965GQK-0000-P equivalent, key selection criteria include VR13.HC compliance, dual-rail phase assignment flexibility, AVSBus/PMBus programmability, non-linear transient response tuning, and integrated current/voltage/temperature telemetry with fault logging.
Technical Context
The MP2965 implements a unified digital control loop that handles both steady-state regulation and load transients without mode switching - eliminating complex analog compensation networks. Its non-linear control algorithm reduces output overshoot during rapid load steps while maintaining tight DC load-line accuracy (±1% IIN sense error, ±1mV VFB comparator offset).
It features two independent feedback paths: Rail 1 uses CS_SUM1 + VDIFF1/VFB1 for droop-based current sensing and remote sensing, while Rail 2 employs CS_SUM2 + VDIFF2/VFB2 with separate DAC-set OCP thresholds (0.17–2.72V range). Both rails support programmable UVLO/OVP/UVP/OCP/OTP with configurable latch/retry/hiccup responses.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Control Architecture | Dual-loop digital PWM with unified non-linear transient/steady-state control - eliminates need for separate compensation networks. |
| Max Phase Count | Rail 1: 7-phase; Rail 2: 3-phase - enables scalable VR design for CPU core + GPU or I/O rail partitioning. |
| Switching Frequency | Up to 3MHz - supports ultra-low-inductance designs and reduces output capacitor count in high-current VRs. |
| PMBus Interface | 10–1000kHz operation with password/pin write protection - enables secure runtime configuration and telemetry reporting. |
| EEPROM Capacity | On-chip non-volatile memory stores full device configuration including phase mapping, protection thresholds, and load-line settings. |
| Current Sensing | IMON1/IMON2 analog outputs (1:16 A/A gain) + CS1–CS7 inputs - provides per-phase and summed current monitoring for thermal balancing. |
| Protection Suite | UVLO (2.68–2.98V), OVP/UVP (±140–300mV relative to DAC), OTP (130°C latch), OCP (programmable 0.17–2.72V threshold). |
Pinout & Package
MP2965GQK-0000-P is housed in a RoHS-compliant QFN-48 package (6mm × 6mm, 0.4mm pitch) with exposed thermal pad. Pin assignments are validated per Monolithic Power Systems Rev. 1.01 datasheet (April 2019), supporting dual-rail remote sensing, 7 PWM outputs, PMBus/AVSBUS/SVID interfaces, and dedicated enable/ready/alert signals.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS1–CS7 | Phase current sense inputs | Accept differential current-sense signals from up to 7 Intelli-Phase phases; unused pins tied to CS_SUM1/CS_SUM2. |
| VFB1/VFB2 | Droop feedback outputs | Source current proportional to load current (IDROOP1/IDROOP2); set load line via RDROOP1/RDROOP2 resistor to VDIFF1/VDIFF2. |
| PWM1–PWM7 | Tri-state logic-level PWM drivers | Drive Intelli-Phase gate inputs at 0V (low), 3.3V (high), or Hi-Z (mid-state); support phase shedding and active current balancing. |
| SCL_P/SDA_P | PMBus clock/data I/O | Enable configuration read/write, telemetry polling (voltage/current/power/temp), and fault logging via standard PMBus v1.3 commands. |
| VOSEN1/VORTN1 & VOSEN2/VORTN2 | Differential remote sense pairs | Direct connection to CPU/GPU VR output and ground at load point - eliminates PCB IR drop errors in high-current applications. |
Key Features
| Feature | Design Value |
|---|---|
| Automatic loop compensation | Eliminates external RC networks; digital tuning adapts to component tolerances and temperature drift across operating conditions. |
| Phase-to-phase active current balancing | Programmable current-offset adjustment per phase ensures thermal uniformity across multi-phase power stages. |
| AVSBus & SVID compatibility | Supports dynamic voltage scaling and telemetry exchange with Intel CPUs using AVSBus (≤3.3V) or SVID (1.05V) protocols. |
| Overshoot reduction via non-linear control | Reduces peak voltage deviation during 200A/µs load steps by >40% vs. conventional PID controllers - minimizes required bulk capacitance. |
| Digital load-line regulation | Configurable droop slope (via VFB-VDIFF resistor) maintains precise VOUT vs. IOUT relationship for VR13.HC compliance. |
Applications
| Server Core Voltage Regulation | GPU Core Regulator |
|---|---|
Use Scenario: High-current, low-voltage CPU core supply in dual-socket x86 servers requiring VR13.HC compliance and AVSBus telemetry. IC Role / Device Role / Timing Role: Dual-loop digital controller managing 7-phase Rail 1 (1.82V @ 228A) and 1-phase Rail 2 (0.95V @ 15A) with synchronized soft-start and thermal throttling. Use Value: Enables <1.5% load-line error and <50µs transient recovery under 200A/µs step loads - meeting Intel's VR13.HC specification for server-class processors. |
Use Scenario: Discrete graphics card VRM powering NVIDIA/AMD GPU cores with dynamic voltage/frequency scaling. IC Role / Device Role / Timing Role: Configured in PVID mode with 3-bit VID control (0.6–0.95V range) and AVSBus communication for real-time GPU power state negotiation. Use Value: Supports over-clocking mode and line-floating detection - allows safe voltage margining during GPU boost states without violating OVP thresholds. |
| Telecom Base Station PSU | High-Density Networking Switch |
Use Scenario: Multi-rail power delivery for FPGA-based baseband processing units in 5G macrocell radios. IC Role / Device Role / Timing Role: Rail 1 powers FPGA core (1.2V @ 120A), Rail 2 supplies I/O banks (1.8V @ 30A); both monitored via IMON1/IMON2 and VTEMP for thermal derating. Use Value: Integrated input current sensing (IIN_SENN/IIN_SENP) and VIN UVLO (adjustable 9–10V) ensure stable operation under fluctuating -48V DC/DC converter output. |
Use Scenario: Compact 1RU switch with ASIC-powered line cards requiring isolated, telemetry-rich VRMs. IC Role / Device Role / Timing Role: Dual-output controller driving 6+1 phase topology: Rail 1 for switch ASIC core, Rail 2 for SerDes PHY - coordinated via shared PMBus bus. Use Value: EEPROM-stored configurations allow field-upgradable VR profiles; PMBus write protection prevents unauthorized firmware tampering in managed infrastructure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output digital VR controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6381IRZ-T7A | Analog-digital hybrid architecture; no on-chip EEPROM; max 6-phase per rail; 1MHz max switching frequency. | Lacks AVSBus support and non-linear transient control; requires external DACs for load-line tuning. | Preferred where legacy analog design familiarity and lower BOM cost outweigh need for digital configurability and AVSBus integration. |
| TPS53689TSSR | TI's C2000-based digital controller; supports up to 8-phase per rail; includes integrated MOSFET drivers; no AVSBus interface. | Requires external PMBus-to-AVSBus bridge IC for Intel CPU compatibility; higher pin count (64-QFN). | Selected when co-location of driver + controller is prioritized, and system-level AVSBus bridging is acceptable. |
Compared with ISL6381IRZ-T7A and TPS53689TSSR, MP2965GQK-0000-P uniquely combines VR13.HC/AVSBus native support, unified non-linear control, and on-chip EEPROM - reducing external components and enabling true plug-and-play VR configuration in Intel-centric platforms.
Availability
MP2965GQK-0000-P is available at Aetrix Electronics and suitable for server motherboard development, GPU reference designs, telecom base station power systems, and high-density networking switches requiring stable component supply and long-term lifecycle support.
Supply support for MP2965GQK-0000-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and mixed-signal ICs for power management, motion control, and automotive applications.
The MP2965 belongs to MPS's VR controller product line, engineered specifically for Intel VR13.HC, AVSBus, and PVID-compliant CPU/GPU power delivery - emphasizing digital configurability, thermal resilience, and minimal external component count.
FAQ
What is the function of the VDIFF1 and VDIFF2 pins?
VDIFF1 and VDIFF2 are differential remote sense amplifier outputs for Rail 1 and Rail 2 respectively. They generate a voltage proportional to the sensed output current (IDROOP1/IDROOP2), which flows through an external RDROOP resistor between VDIFF and VFB to establish the load-line droop characteristic required by VR13.HC specifications.
Can MP2965GQK-0000-P operate without an external EEPROM?
Yes - MP2965GQK-0000-P contains on-chip EEPROM that stores all configuration registers, protection thresholds, and phase assignments. No external non-volatile memory is required; factory-programmed or user-defined settings persist across power cycles.
How does the auto phase-shedding feature improve efficiency?
Auto phase-shedding dynamically disables inactive PWM outputs under light load conditions while maintaining regulation accuracy. This reduces switching losses and gate drive power, improving overall VR efficiency by up to 8% at 10% load compared to fixed-phase operation - verified in 6+1-phase server VRM test setups.
What is the maximum supported AVSBus voltage level?
The AVSBus interface supports two voltage modes: ≤1.8V (using AVS_MOSI/AVS_MISO) and 1.8V–3.3V (using AVS_MISO_HV). The controller automatically detects bus voltage and configures internal level shifters - enabling direct interfacing with Intel CPUs across multiple generations without external translators.
Does MP2965GQK-0000-P support both SVID and AVSBus simultaneously?
No - SVID and AVSBus are mutually exclusive interface modes selected at boot via hardware strapping (ALT# pin state). The device operates in either SVID (for legacy VR12/VR13) or AVSBus (for VR13.HC) mode, but not both concurrently. Configuration is locked after power-on reset.
What thermal monitoring capability does MP2965 provide?
MP2965 monitors VR temperature via the VTEMP analog input, which accepts the maximum voltage from a daisy-chained bus of Intelli-Phase temperature sensors. It triggers VRHOT# assertion when the derived junction temperature exceeds the programmed threshold (default 130°C), supporting latch-off or hiccup-mode thermal shutdown.
How is input voltage monitoring implemented?
Input voltage is monitored using the IIN_SENP/IIN_SENN differential pair, which connects across an external current-sense resistor. The controller converts sensed input current into an analog IIN output (1:16 A/A gain) and supports programmable VIN UVLO thresholds (9–10V) via PMBus register 0x35h for brown-out protection.
MP2965GQK-0000-P Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Monolithic Power Systems Inc.
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Controller, Intel VR13
- Voltage - Input:
- 3V ~ 3.6V
- Number of Outputs:
- 2
- Voltage - Output:
- -
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-QFN (6x6)
MP2965GQK-0000-P FAQ
1.How can I place an order for MP2965GQK-0000-P through Aetrix?
Please submit a Request for Quotation (RFQ) for MP2965GQK-0000-P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MP2965GQK-0000-P reliable?
The price and inventory of MP2965GQK-0000-P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MP2965GQK-0000-P is usually 5 days.
3.What payment methods are accepted for MP2965GQK-0000-P?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MP2965GQK-0000-P transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MP2965GQK-0000-P?
MP2965GQK-0000-P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MP2965GQK-0000-P order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MP2965GQK-0000-P?
For technical support, including MP2965GQK-0000-P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MP2965GQK-0000-P requirements.
6.How does Aetrix verify that MP2965GQK-0000-P is sourced from the original manufacturer or authorized distributors?
All MP2965GQK-0000-P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MP2965GQK-0000-P meets industry standards.
7.What is the process for return or replacement of MP2965GQK-0000-P?
All MP2965GQK-0000-P units undergo pre-shipment inspection (PSI). If there is an issue with MP2965GQK-0000-P, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MP2965GQK-0000-P part is unused and in its original packaging.
Return procedure for MP2965GQK-0000-P:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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