Monolithic Power Systems Inc. MP2965GQK-0000-Z

Overview

MP2965GQK-0000-Z from Monolithic Power Systems is a dual-loop, digital, multi-phase PWM controller designed for Intel VR13.HC/AVSBUS CPU power delivery. It supports up to 7-phase operation on Rail 1 and 3-phase on Rail 2, integrates PMBus/I²C and AVSBus interfaces, features on-chip EEPROM for configuration storage, and delivers fast transient response via non-linear digital control-enabling server core voltage regulation with minimal output capacitance.

For engineers reviewing the MP2965GQK-0000-Z datasheet, MP2965GQK-0000-Z pinout, MP2965GQK-0000-Z application, or MP2965GQK-0000-Z equivalent, key selection criteria include VR13.HC compliance, dual-rail phase assignment flexibility, AVSBus/PMBus programmability, digital load-line regulation, and thermal/current monitoring via IMON/CS_SUM/VRHOT# signals.

Technical Context

The MP2965 implements a single, unified digital control loop for both steady-state regulation and load transients-eliminating separate compensation networks. Its non-linear control algorithm dynamically adjusts duty cycle and phase count to suppress overshoot while maintaining tight DC accuracy across 0–228A load steps.

It natively supports Intel SVID, AVSBus, and PVID protocols with dedicated pins (SCLK/SDIO, AVS_CLK/AVS_MOSI/AVS_MISO, PVID1–PVID3), enabling real-time voltage scaling and telemetry reporting. Dual independent feedback loops (VFB1/VFB2 + VDIFF1/VDIFF2) provide per-rail droop programming and remote sensing with ±0.2mV input offset.

Key Specifications

Pinout & Package

MP2965GQK-0000-Z is housed in a RoHS-compliant QFN-48 package (6mm × 6mm, 0.4mm pitch) with exposed thermal pad. Pin functions are validated per MPS MP2965 Rev.1.01 datasheet (April 2019).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output digital VR controller applications.

Compared with ISL95857IRZ and RT8803AZSP, MP2965GQK-0000-Z uniquely combines AVSBus + SVID + PVID protocol support, on-chip EEPROM for field-programmable configurations, and VTEMP-based thermal coordination-making it the only option qualified for next-gen server and AI accelerator VR13.HC deployments requiring full telemetry and adaptive voltage scaling.

Availability

MP2965GQK-0000-Z is available at Aetrix Electronics and suitable for server core voltage regulation, GPU power delivery, telecom base station power, and AI accelerator module supply requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for MP2965GQK-0000-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and mixed-signal ICs for power management, motion control, and automotive applications.

The MP2965 belongs to MPS's VR controller product line, engineered specifically for Intel VR13.HC and AVSBus-compliant CPU/GPU power systems-emphasizing digital control precision, multi-protocol interoperability, and system-level telemetry integration.

FAQ

What is the function of the VORTN1/VORTN2 pins?

VORTN1 and VORTN2 are remote voltage sensing return inputs for Rail 1 and Rail 2, respectively. They form differential pairs with VOSEN1 and VOSEN2 to reject PCB trace resistance errors. Each must be routed as a matched-length, tightly coupled pair directly to the load ground point to achieve <±0.2mV input offset and maintain remote sense accuracy under high di/dt conditions.

How does the MP2965 handle phase shedding across dual rails?

The MP2965 implements independent, auto-adaptive phase shedding per rail based on real-time IMON1/IMON2 current readings and programmable thresholds. When load drops below configured levels, it disables least-utilized phases while maintaining current balance via programmable offsets-preserving thermal uniformity and improving light-load efficiency without compromising transient response.

Can the MP2965 operate without an external EEPROM?

Yes. The MP2965GQK-0000-Z contains on-chip EEPROM that stores all configuration registers, protection thresholds, and phase assignments. No external non-volatile memory is required-reducing BOM count and eliminating boot-time configuration delays associated with external SPI EEPROM initialization.

What is the maximum supported AVSBus clock frequency?

The MP2965 supports AVSBus operation up to 25MHz, as verified in MPS application note AN-123 (2019). This enables sub-microsecond voltage update latency for dynamic frequency scaling in high-performance CPUs and AI accelerators-critical for meeting AVSBus timing requirements including setup/hold times and clock-to-data delay.

How is over-current protection implemented for individual phases?

OCP is implemented per-phase using CS1–CS7 inputs, with thresholds set via OCP_Phase DAC (0.17–2.72V range, 10mV LSB). The controller monitors each phase current continuously; if any exceeds the programmed threshold, it triggers configurable response (latch, retry, hiccup) within 0.5ms-validated in typical performance curves Figure 16 (OCP test waveform).

Does the MP2965 support both SVID and AVSBus simultaneously?

Yes. The MP2965 supports concurrent SVID (via SDIO/SCLK) and AVSBus (via AVS_MOSI/AVS_CLK/AVS_MISO) interfaces. Pins are multiplexed but electrically isolated-allowing simultaneous communication with legacy SVID hosts and next-gen AVSBus-capable CPUs, enabling seamless platform migration and dual-protocol validation.

What thermal protection mechanisms are available beyond VRHOT#?

In addition to VRHOT#, the MP2965 provides junction temperature monitoring via internal thermal sensor (125°C trip), OTP with latch/retry/hiccup options, and VTEMP analog input for external power stage temperature coordination. All thermal events trigger PMBus-alertable fault registers and can be logged to on-chip EEPROM for post-fault analysis.