Monolithic Power Systems Inc. MP3326GR-Z

Overview

MP3326GR-Z from Monolithic Power Systems is a 16-channel WLED driver IC with integrated current sinks, I²C interface, and independent PWM + analog dimming per channel. It operates from 4V to 16V input, delivers up to 50mA per channel (VIN ≥ 4.5V), supports 12-bit PWM and 6-bit analog dimming, and features open-load/short/over-temperature protection. It is used in automotive instrument clusters for precise multi-zone backlight control.

For engineers reviewing the MP3326GR-Z datasheet, MP3326GR-Z pinout, MP3326GR-Z application, or MP3326GR-Z equivalent, key selection considerations include per-channel dimming resolution, cascaded I²C address configuration (10 options), RFSH/FLT dual-mode functionality (refresh sync or fault flag), LED current slew rate programmability (5–20 µs), and thermal shutdown threshold (170°C).

Technical Context

The MP3326GR-Z implements 16 matched current-sink channels with external ISET resistor programming and internal 12-bit PWM counters plus 6-bit DAC-based analog dimming. Its I²C controller supports register-level channel enable/disable, dimming value write, protection mode selection (hiccup/latch-off), and refresh frequency configuration via FRFSH[9:0].

Protection logic integrates voltage-based LED open-detection (100–160 mV threshold, 4 ms delay) and configurable short-detection (2–5 V thresholds), with fault status reported via open-drain RFSH/FLT and dedicated register bits. Phase-shifted PWM timing (40 µs inter-channel delay) and programmable current slew rate reduce EMI in high-density LED arrays.

Key Specifications

Pinout & Package

MP3326GR-Z is housed in a thermally enhanced QFN-24 package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad for PCB heat dissipation. Pin 14 is GND; pin 24 is VIN; pins 7–23 are LEDx cathode current sinks (x = 1 to 16); pin 6 is ISET; pins 3–5 are SCL, SDA, ADDR; pin 1 is RFSH/FLT; pin 2 is EN.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-channel LED driver applications.

Compared with IS31FL3729-QFLS4 and MAX20052ATP/V+T, the MP3326GR-Z uniquely combines per-channel analog+PWM dimming, RFSH/FLT dual-mode timing/fault signaling, and programmable EMI-reduction features-making it optimal for automotive and medical displays demanding flicker-free operation and robust fault handling.

Availability

MP3326GR-Z is available at Aetrix Electronics and suitable for automotive instrument clusters, industrial HMI displays, RGB indicator arrays, and medical device UI panels requiring stable component supply across extended product lifecycles.

Supply support for MP3326GR-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP3326 belongs to MPS's high-channel-count LED driver product line, engineered specifically for automotive-grade backlighting and industrial display applications requiring precision dimming, robust fault protection, and EMI-compliant operation.

FAQ

What is the maximum number of MP3326GR-Z devices that can be cascaded on a single I²C bus?

Up to 10 MP3326GR-Z devices can be cascaded on one I²C bus. Each device supports 10 unique I²C addresses (0x30–0x39) configured via the ADDR pin resistor divider. No external address jumpers or hardware modifications are required-address selection is fully resistor-programmable and stable across temperature.

How does the RFSH/FLT pin function in dual-mode operation?

The RFSH/FLT pin operates in two mutually exclusive modes controlled by the FLTEN bit (Register 0x01, bit 7). When FLTEN = 0, it outputs a programmable refresh signal (0–300 Hz) synchronized to PWM timing. When FLTEN = 1, it becomes an active-low open-drain fault flag pulled low on any detected open-load, short-circuit, or over-temperature event.

Can analog and PWM dimming be used simultaneously on the same channel?

Yes-each of the 16 channels supports concurrent analog and PWM dimming. The analog dimming register (ICHx, 6-bit) scales the full-scale LED current set by RISET, while the PWM register (PWMx, 12-bit) modulates that scaled current. The resulting output is the product of both values, enabling ultra-fine brightness control across >18-bit effective resolution.

What is the purpose of the 40 µs phase shift feature, and how is it enabled?

The 40 µs phase shift staggers PWM rising edges across consecutive LED channels (e.g., CH2 starts 40 µs after CH1), reducing peak input current and conducted EMI. It is enabled by setting PS_EN = 1 (Register 0x01, bit 1) and requires no additional timing circuitry-fully implemented in silicon with deterministic delay.

Does the MP3326GR-Z support latch-off or hiccup mode for fault recovery?

Yes-the LATCH bit (Register 0x01, bit 6) selects fault response mode. When LATCH = 1, the device enters latch-off mode: faulted channels remain disabled until VIN or EN is cycled. When LATCH = 0, it enters hiccup mode: faulted channels retry every 1 ms for 32 µs to detect fault clearance, allowing automatic recovery without system reset.

What is the minimum external ISET resistor value required for 50 mA per channel operation?

For 50 mA per channel at VIN ≥ 4.5 V, the recommended ISET resistor is 10 kΩ. This yields VISET ≈ 1.2 V (per datasheet), resulting in ILED = (VISET / RISET) × (63 / 63) = 1.2 V / 10 kΩ = 120 µA × 63 = 7.56 mA base, scaled to 50 mA via register ICHx = 0x3F. Actual RISET depends on target current and dimming range-20 kΩ gives ~25 mA nominal.

Is the thermal pad on the QFN-24 package electrically connected, and how should it be handled on the PCB?

Yes-the exposed thermal pad on the MP3326GR-Z QFN-24 package is internally connected to GND. It must be soldered to a solid copper thermal pad on the PCB, connected via ≥4 thermal vias (0.3 mm diameter) to inner-layer or back-side ground planes to ensure θJA ≤ 42 °C/W and reliable operation at full load.