Monolithic Power Systems Inc. MP3423GG-P

Overview

MP3423GG-P from Monolithic Power Systems is a synchronous step-up DC-DC converter with true output disconnect, designed for battery-powered systems requiring 5V/3.1A output from 2.8V–4.2V input. It integrates 9A NMOS and 16mΩ PMOS switches, operates at 600kHz fixed frequency, delivers up to 98% efficiency, and features inrush current limiting, OCP/SCP/OVP/OTP protection, and internal soft-start and compensation.

For engineers reviewing the MP3423GG-P datasheet, MP3423GG-P pinout, MP3423GG-P application, or MP3423GG-P equivalent, key selection criteria include its 1.9V–5.5V input range, 2.5V–5.5V programmable output, 43µA quiescent current, 2×2mm QFN-14 package with thermal pad, and true output disconnect enabling zero-VOUT shutdown in portable power banks and USB supply designs.

Technical Context

The MP3423GG-P implements fixed-frequency (600kHz) current-mode PWM control with internal slope compensation and an error amplifier referenced to 807mV. Its dual-MOSFET architecture supports three operational modes-linear charge (VOUT < 1.7V), buck (VOUT < VIN + 0.3V), and boost (VOUT ≥ VIN + 0.3V)-with mode transitions governed by real-time voltage comparisons and current limiting thresholds.

Startup begins with linear charging of the output capacitor via the PMOS rectifier (0.2A–0.7A current-limited), then transitions to closed-loop boost operation once VOUT reaches 1.7V. During shutdown, the PMOS gate is actively controlled to eliminate body diode conduction, ensuring complete output isolation and preventing backfeed into the input rail.

Key Specifications

Pinout & Package

MP3423GG-P is housed in a thermally enhanced 14-pin QFN package measuring 2mm × 2mm with exposed thermal pad (JEDEC MO-220 compliant). The package supports high-power density layouts and requires solder paste stencil design per MPS land pattern recommendations.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous step-up converter applications.

Compared with TPS61088RHLR and RT9086AGQW, MP3423GG-P uniquely combines true output disconnect, internal compensation, and 43µA quiescent current in a 2×2mm package - making it optimal for battery-backed USB ports and energy-sensitive portable accessories where standby leakage and physical size are primary constraints.

Availability

MP3423GG-P is available at Aetrix Electronics and suitable for USB power delivery adapters, wireless earbud charging cases, and portable Bluetooth speakers requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for MP3423GG-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP3423 belongs to MPS's high-efficiency DC-DC boost converter product line, engineered specifically for space-constrained, battery-powered consumer electronics demanding low IQ, true output disconnect, and robust protection in minimal footprint.

FAQ

What is the minimum input voltage required for MP3423GG-P to start switching?

The MP3423GG-P starts switching after completing linear charge mode, which initiates when input voltage exceeds the rising UVLO threshold of 1.3V (typical). However, reliable regulation at 5V output requires ≥2.8V input per the typical application circuit; below this, output current capability degrades due to duty cycle and switch current limits.

Does MP3423GG-P require external compensation components?

No. The MP3423GG-P features an internally compensated error amplifier optimized for standard 1.5µH inductors and 22µF ceramic output capacitors. No external compensation network is needed - simplifying layout and reducing bill-of-materials cost in consumer-grade designs.

How does the true output disconnect function protect downstream circuitry?

During shutdown (EN = low), the internal PMOS gate is actively pulled to prevent body diode conduction. This blocks reverse current flow from VOUT to VIN, allowing external circuits to maintain independent bias or discharge safely - critical for USB OTG devices and battery backup systems where backfeed could damage host controllers or drain primary cells.

Can MP3423GG-P operate with input voltage higher than output voltage?

Yes - the MP3423GG-P automatically enters buck mode when VOUT < VIN + 0.3V, limiting peak switch current to 4A (vs. 9A in boost mode). This feature supports safe startup and short-circuit recovery but is not intended for continuous buck operation due to reduced efficiency and regulation accuracy.

What is the recommended output capacitor configuration for EMI reduction?

MPS recommends placing a 1µF ceramic capacitor directly between OUT and PGND pins, in parallel with bulk output capacitance (≥22µF). This local decoupling capacitor suppresses high-frequency SW node spikes, reduces conducted EMI, and improves transient response - especially critical in USB-IF compliant designs.

Is the NC pin (Pin 7) required to be grounded in the application layout?

No - Pin 7 (NC) is reserved for factory testing and has no electrical function. The datasheet explicitly states it may be left floating or connected to PGND; neither choice affects performance, thermal behavior, or reliability in production designs.

How does the linear charge mode prevent inrush current during cold start?

At startup, the MP3423GG-P uses the internal PMOS as a linear regulator to charge the output capacitor, limiting current to 0.2A initially (at VOUT = 0V) and ramping to 0.7A at VOUT = 1.7V. This controlled ramp avoids instantaneous current surges that could collapse weak battery sources or trigger overcurrent protection in upstream power paths.