My Inquiry
My Account
Monolithic Power Systems Inc. MP3423GG-Z
_-_-14.jpg)
- Part No.:
- MP3423GG-Z
- Manufacturer:
- Monolithic Power Systems Inc.
- Package:
- 14-PowerVFQFN
- Datasheet:
-
MP3423GG-Z.pdf
- Description:
- IC REG BOOST ADJ 9A 14QFN
- Quantity:
- Payment:
- Shipping:
Inventory:7,245
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MP3423GG-Z from Monolithic Power Systems is a synchronous step-up DC-DC converter with true output disconnect, designed for battery-powered 5V rail generation from inputs as low as 1.9V. It delivers up to 3.1A at 5V output with 98% peak efficiency, features integrated 11mΩ NMOS and 16mΩ PMOS switches, and operates at a fixed 600kHz switching frequency in a thermally enhanced 2×2mm QFN-14 package.
For engineers reviewing the MP3423GG-Z datasheet, MP3423GG-Z pinout, MP3423GG-Z application, or MP3423GG-Z equivalent, key selection criteria include input UVLO thresholds (1.3V rising), output disconnect capability during shutdown, 9A switch current limit, 43µA quiescent current in normal operation, and internal soft-start with 2ms reference ramp time - all critical for portable power bank and USB supply designs requiring low-noise, high-efficiency boost conversion.
Technical Context
The MP3423GG-Z implements fixed-frequency current-mode PWM control with internal slope compensation and an error amplifier referenced to 807mV. Its dual-mode startup sequence includes linear charge (0–1.7V), step-down mode (VOUT < VIN + 0.3V), and full boost mode (VOUT ≥ VIN + 0.3V), enabling robust inrush limiting and short-circuit recovery.
True output disconnect is achieved via controlled turn-off of the internal P-channel rectifier, eliminating body diode conduction and allowing VOUT to fully discharge to 0V during shutdown. Protection includes overvoltage lockout at 7V, thermal shutdown at 150°C with 20°C hysteresis, and cycle-by-cycle current limiting with 9A typical switch current threshold.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 1.9V to 5.5V - supports single-cell Li-ion (2.8–4.2V) and Li-polymer batteries with margin for voltage sag. |
| Output Voltage Range | 2.5V to 5.5V - programmable via external resistor divider on FB pin; enables USB 5V compliance and flexible system rail generation. |
| Switching Frequency | 600kHz (±100kHz) - enables compact 1–2.2µH inductors and reduces EMI filtering burden vs. lower-frequency boosters. |
| Peak Switch Current Limit | 9A typical - supports high-output-current applications like 5V/3.1A power banks without external current sensing. |
| Quiescent Current | 43µA at 3.3V IN, 5V OUT - minimizes standby drain in always-on battery backup systems. |
| Efficiency | Up to 98% - achieved via synchronous rectification with 11mΩ NMOS and 16mΩ PMOS, eliminating Schottky loss. |
| Output Disconnect | True - PMOS gate fully isolates OUT from IN during EN=low, preventing backfeed and enabling zero-VOUT shutdown. |
Pinout & Package
MP3423GG-Z is housed in a thermally optimized 2mm × 2mm, 14-pin QFN package with exposed thermal pad (JEDEC MO-220 compliant). The package supports high-power density layouts and efficient heat dissipation via PCB copper area under the exposed paddle.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 13 | PGND | Power ground return for high-current paths (SW, OUT); must connect directly to large copper pour for thermal and EMI performance. |
| 3, 14 | SW | Switch node connecting internal NMOS/PMOS drains; requires shortest possible trace to inductor to minimize ringing and EMI. |
| 4, 5, 6 | OUT | Boost output node; internally connected to PMOS drain; fully disconnected from IN during shutdown; feeds output capacitor bank. |
| 7 | NC | No-connect pin reserved for factory use; must be left floating or tied to PGND per layout guidelines. |
| 8 | EN | Active-high enable input; logic threshold 1.2V high / 0.4V low; controls full device startup/shutdown and output disconnect state. |
| 9 | IN | Main input supply; powers internal bias during startup; transitions to OUT-derived bias once VOUT exceeds VIN. |
| 10 | INA | Factory bias pin; must be externally connected to IN in all applications per datasheet requirement. |
| 11 | AGND | Analog ground reference for feedback amplifier; separate from PGND to reduce noise coupling into FB loop. |
| 12 | FB | Feedback input for output voltage regulation; senses resistor divider tap; internal 807mV reference sets VOUT = 0.807V × (1 + R1/R2). |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Synchronous Rectification | Eliminates external Schottky diode and associated conduction losses; enables >95% efficiency at light loads due to active PMOS control. |
| Internal Soft-Start & Compensation | 2ms reference ramp time prevents output overshoot; eliminates need for external compensation network or soft-start capacitor. |
| Inrush & Short-Circuit Protection | Linear charge mode limits startup current to 0.2–0.7A; automatic transition to step-down mode below VIN+0.3V enhances fault recovery. |
| Full Thermal & Electrical Protection | Includes OVP (7V), OTP (150°C), SCP, and OCP - all implemented in hardware with no external components required. |
| True Output Disconnect | Zero-VOUT capability during shutdown isolates downstream circuits, prevents backfeed, and enables safe hot-swap or battery replacement. |
Applications
| Power Bank Charging Circuit | USB-C Power Delivery Sink |
|---|---|
|
Use Scenario: Boosting single-cell Li-ion (2.8–4.2V) to regulated 5V for charging smartphones or tablets via USB-A ports. IC Role / Device Role / Timing Role: Primary synchronous boost controller managing input-to-output voltage translation, load transient response, and battery discharge optimization. Use Value: Delivers 3.1A at 5V with <100mV load regulation error and 43µA quiescent current, extending usable battery capacity by >12% versus non-synchronous alternatives. |
Use Scenario: Providing stable 5V bus for USB-C PD sink applications where host negotiation requires fast, low-noise voltage establishment. IC Role / Device Role / Timing Role: Regulated 5V rail generator with true disconnect ensuring clean VBUS ramp-up/down during PD contract changes. Use Value: Internal 600kHz switching and soft-start ensure VBUS settles within 2ms of EN assertion, meeting USB PD specification timing for source/sink handshaking. |
| Wireless Headphone Battery Backup | Portable Medical Sensor Hub |
|
Use Scenario: Maintaining 5V USB power for firmware updates or diagnostics when main battery drops below 3.0V. IC Role / Device Role / Timing Role: Secondary boost stage activated only during low-battery maintenance mode, isolated via EN control. Use Value: 1.9V minimum start-up voltage allows operation down to deeply discharged cells; output disconnect prevents reverse leakage into depleted battery. |
Use Scenario: Powering 5V analog front-end and BLE radio from coin-cell or small Li-polymer in handheld diagnostic devices. IC Role / Device Role / Timing Role: High-efficiency boost regulator with ultra-low IQ and precise output regulation for sensitive analog signal chains. Use Value: 98% peak efficiency and 807mV FB reference tolerance (±1.5%) ensure stable sensor bias rails with <1mV ripple, preserving ADC accuracy. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous boost converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS61088RHLR | 6.5V max input, 12A switch limit, 2.5MHz switching, no true output disconnect (body diode conduction remains) | Better suited for high-frequency, space-constrained designs; unsuitable where zero-VOUT shutdown is mandatory | Select if board area is constrained and output disconnect is not required; avoid where backfeed isolation is critical |
| LT3467EDD#TRPBF | 1.2MHz switching, 2A switch limit, external MOSFETs required, no integrated PMOS disconnect | Requires additional FETs and gate drivers; higher BOM count but offers design flexibility for custom topologies | Choose for designs needing adjustable frequency or discrete switch optimization; not drop-in for MP3423GG-Z footprint |
Compared with TPS61088RHLR and LT3467EDD#TRPBF, MP3423GG-Z uniquely combines true output disconnect, 9A current capability, and 43µA quiescent current in a 2×2mm QFN - making it optimal for compact, battery-isolated 5V boost applications where safety, efficiency, and minimal external components are prioritized.
Availability
MP3423GG-Z is available at Aetrix Electronics and suitable for power banks, USB-C accessory power supplies, and portable medical sensor hubs requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for MP3423GG-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with over two decades of leadership in DC-DC conversion, motor drivers, and LED lighting controllers.
The MP3423 belongs to MPS's high-efficiency synchronous boost converter product line, engineered specifically for portable battery-powered systems demanding ultra-low IQ, true output isolation, and minimal external component count.
FAQ
What is the minimum input voltage required for MP3423GG-Z to start switching?
The MP3423GG-Z begins startup when the IN pin voltage exceeds the rising UVLO threshold of 1.3V (typical), and enters linear charge mode until the output reaches 1.7V. Full PWM switching commences only after VOUT ≥ 1.7V and VOUT ≥ VIN + 0.3V, ensuring reliable cold-start from weak or deeply discharged batteries down to 1.9V nominal operation.
Does MP3423GG-Z require an external Schottky diode?
No. The MP3423GG-Z integrates both NMOS and PMOS power switches, including a synchronous rectifier with true disconnect capability. Adding an external Schottky diode would defeat the output disconnect function and introduce conduction loss, violating the recommended application circuit per the datasheet.
How is output voltage programmed on MP3423GG-Z?
VOUT is set using a resistor divider from OUT to PGND, with the midpoint connected to the FB pin. The internal 807mV reference yields VOUT = 0.807V × (1 + R1/R2). For 5V output, R1 = 787kΩ and R2 = 150kΩ are specified in the typical application; R1 ≥ 600kΩ is recommended for stability and low IQ.
What thermal derating applies to MP3423GG-Z in a standard 4-layer PCB layout?
With θJA = 80°C/W on a JEDEC JESD51-7 4-layer board, the MP3423GG-Z dissipates up to 1.56W continuously at 25°C ambient. At 85°C ambient, maximum allowable power drops to ~0.95W - corresponding to ~2.2A at 5V output. Layout with thermal vias under the exposed paddle is essential to maintain junction temperature ≤125°C under full load.
Can MP3423GG-Z operate in buck mode?
Yes - during startup or overload, the MP3423GG-Z automatically enters step-down mode when VOUT < VIN + 0.3V, using the PMOS as a pass element with 4A typical current limit. However, this mode is intended only for transient conditions; sustained operation in buck mode degrades regulation and increases thermal stress due to higher conduction loss.
Is the NC pin (Pin 7) required to be grounded?
No. Pin 7 is designated NC (No Connect) and reserved for factory use. The datasheet explicitly states it may be left floating or connected to PGND - neither choice affects functionality. Grounding it adds no benefit but avoids potential routing conflicts in dense layouts.
What protection features are implemented in hardware without external components?
All protections - overvoltage (7V), overtemperature (150°C shutdown with 20°C hysteresis), overcurrent (9A switch limit), short-circuit (linear charge + step-down mode fallback), and input UVLO (1.3V rising) - are fully integrated and require no external resistors, capacitors, or sense elements. These functions are verified in silicon and active across the full operating temperature range.
MP3423GG-Z Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Monolithic Power Systems Inc.
- Series:
- -
- Package/Case:
- 14-PowerVFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Up
- Output Configuration:
- Positive
- Topology:
- Boost
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 1.9V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 2.5V
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 9A (Switch)
- Frequency - Switching:
- 600kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-QFN (2x2)
MP3423GG-Z FAQ
1.How can I place an order for MP3423GG-Z through Aetrix?
Please submit a Request for Quotation (RFQ) for MP3423GG-Z on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MP3423GG-Z reliable?
The price and inventory of MP3423GG-Z are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MP3423GG-Z is usually 5 days.
3.What payment methods are accepted for MP3423GG-Z?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MP3423GG-Z transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MP3423GG-Z?
MP3423GG-Z orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MP3423GG-Z order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MP3423GG-Z?
For technical support, including MP3423GG-Z datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MP3423GG-Z requirements.
6.How does Aetrix verify that MP3423GG-Z is sourced from the original manufacturer or authorized distributors?
All MP3423GG-Z products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MP3423GG-Z meets industry standards.
7.What is the process for return or replacement of MP3423GG-Z?
All MP3423GG-Z units undergo pre-shipment inspection (PSI). If there is an issue with MP3423GG-Z, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MP3423GG-Z part is unused and in its original packaging.
Return procedure for MP3423GG-Z:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MP3423GG-Z Tags
-
TPS562201DDCR
Texas Instruments
-
MC34063ABD-TR
STMicroelectronics
-
TPS561201DDCR
Texas Instruments
-
MC33063ADR
Texas Instruments
-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments
-
AP3012KTR-G1
Diodes Incorporated
-
TLV61048DBVR
Texas Instruments
-
AZ34063UMTR-G1
Diodes Incorporated
-
TPS562200DDCR
Texas Instruments
-
AP62300TWU-7
Diodes Incorporated
-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
