Monolithic Power Systems Inc. MP3428AGL-P

Overview

MP3428AGL-P from Monolithic Power Systems is a 600kHz, current-mode synchronous boost converter with integrated 10mΩ low-side MOSFET, input disconnect capability, and programmable input average current limit. It operates from 3V to 20V input, delivers up to 22V output, supports 19A internal switch current limit, and targets high-current portable power applications including power banks, Thunderbolt interfaces, and Bluetooth audio systems.

For engineers reviewing the MP3428AGL-P datasheet, MP3428AGL-P pinout, MP3428AGL-P application, or MP3428AGL-P equivalent, key selection criteria include its 600kHz fixed-frequency operation, QFN-22 (3mm × 4mm) thermal performance, input disconnect function for battery protection, and external compensation for transient optimization across load and line variations.

Technical Context

The MP3428AGL-P implements peak current-mode control with a fixed 600kHz switching frequency and supports both internal current sensing (CLDR = GND) and external R_SENSE-based average current limiting. Its dual-loop protection includes linear charge current limiting during startup and boost-mode input average current regulation once V_OUT > V_IN.

It integrates a synchronous gate driver (SDR) powered by a bootstrap circuit (BST), enabling efficient external synchronous rectification. The device features programmable UVLO hysteresis, soft-start via external capacitor, and thermal shutdown at 150°C with 25°C hysteresis - all coordinated through analog feedback on COMP and FB pins.

Key Specifications

Pinout & Package

MP3428AGL-P is housed in a thermally enhanced QFN-22 package (3mm × 4mm, 0.5mm pitch) with exposed thermal pad. Pin 1 is marked by a dot; top marking includes "MP" prefix, year/week code, "3428A", and lot number.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous boost converter applications.

Compared with RT4801BZQW and TPS61088RHLR, MP3428AGL-P uniquely integrates a dedicated CLDR driver for hardware-enforced input disconnect, supports higher 19A peak current, and maintains fixed 600kHz operation for predictable EMI filtering - making it optimal for high-reliability, battery-sensitive portable power systems.

Availability

MP3428AGL-P is available at Aetrix Electronics and suitable for power banks, Thunderbolt interfaces, and Bluetooth audio systems requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for MP3428AGL-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with a focus on energy-efficient DC-DC conversion and motor control solutions.

The MP3428A product line is designed for high-current, wide-input portable power applications - emphasizing integration (internal 10mΩ FET, SDR, CLDR), protection (input disconnect, OVP, thermal shutdown), and design flexibility (external COMP/SS).

FAQ

What is the purpose of the CLDR pin, and how does it enable input disconnect?

The CLDR pin drives the gate of an external high-side N-channel MOSFET placed between the input source and the boost converter. When the device shuts down or detects an output short, CLDR pulls low, turning off the MOSFET and physically isolating the input - preventing battery drain or upstream supply damage. This is distinct from typical enable-based shutdown, which leaves the input path conductive.

Can MP3428AGL-P operate with only internal current sensing, and what are the trade-offs?

Yes - connect CLDR directly to PGND and SENSE to IN to activate internal current sensing. This eliminates external R_SENSE but fixes the current limit at 19A (typical). External sensing offers programmability (e.g., 5A–15A via R_SENSE) and better accuracy under high-temperature drift, while internal sensing simplifies layout and reduces BOM count.

How does the BST/SDR architecture improve efficiency compared to asynchronous rectification?

The integrated SDR driver provides complementary gate drive to an external low-R_DS(on) N-MOSFET used as the output rectifier, replacing a Schottky diode. With typical 10mΩ FETs, conduction losses drop significantly versus 0.3V–0.5V diode forward voltage - especially at >3A loads - improving full-load efficiency by 3–5% and reducing thermal load on the PCB.

What is the role of the SS pin during startup, and how does it prevent inrush current?

The SS pin accepts an external capacitor charged by a 7µA current. During startup, the COMP voltage is clamped to V_SS + 0.7V, and switching frequency begins at 150kHz (¼ of 600kHz). As V_SS ramps, frequency and COMP clamp rise together - gradually increasing duty cycle and output voltage. This staged ramp limits peak inductor current and input surge to safe levels.

Does MP3428AGL-P support output over-voltage protection, and how is it implemented?

Yes - the FB pin monitors output voltage via resistor divider. If FB exceeds 1.323V (108% of 1.225V reference), the controller immediately halts switching. Once FB falls below 1.275V (104% of reference), normal regulation resumes automatically. This hardware-based OVP operates independently of the main control loop and responds within microseconds.

How is thermal performance managed in the QFN-22 package, and what layout guidance applies?

The QFN-22 (3mm × 4mm) package features an exposed thermal pad soldered to a large copper pour on the PCB. With θ_JA = 48°C/W on a 4-layer board, continuous 2.6W dissipation is supported at 25°C ambient. Layout best practices include connecting all PGND pins and the thermal pad to a solid inner-layer ground plane, using ≥6 thermal vias under the pad, and avoiding signal traces beneath the IC.