Monolithic Power Systems Inc. MP3910GK-Z

Overview

MP3910GK-Z from Monolithic Power Systems is a peak current mode PWM controller for external N-channel MOSFETs in boost, flyback, forward, and SEPIC topologies. It delivers 1A gate drive at 12V, supports programmable switching frequency from 30kHz to 400kHz, features external soft-start via SS pin capacitor, and enters pulse-skipping mode below 0.95V COMP voltage to achieve high light-load efficiency in telecom isolated power supplies and brick modules.

For engineers reviewing the MP3910GK-Z datasheet, MP3910GK-Z pinout, MP3910GK-Z application, or MP3910GK-Z equivalent, this controller's cycle-by-cycle current limit, hiccup-mode OLP/SCP/OVP protection, and dual feedback path (FB or COMP) selection via ISENSE pin are critical for robust offline and isolated DC-DC design validation.

Technical Context

The MP3910GK-Z implements a peak current mode control architecture with integrated slope compensation, enabling stable loop compensation and inherent cycle-by-cycle current limiting. Its error amplifier transconductance is 0.56 mA/V, and COMP output drives up to 75 µA sourcing/sinking current-directly shaping duty cycle in response to FB or optocoupler-derived feedback.

It integrates a 12V internal LDO regulator (VCC) with 4.17V UVLO threshold and 350mV hysteresis, and uses a 54 µA constant-current source to charge the SS capacitor for soft-start and hiccup-timer functions. Protection logic includes 185 mV current-limit threshold, 350 mV SCP trigger, and 1.438 V OVP reference-all referenced to internal precision bandgaps.

Key Specifications

Pinout & Package

The MP3910GK-Z is housed in an MSOP-10 package with exposed thermal pad (pin 10 GATE adjacent to GND pin 1), optimized for high-current gate drive and thermal dissipation in compact power modules.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar peak current mode PWM controller applications.

Compared with UCC28083DR and LM5022MM/NOPB, the MP3910GK-Z uniquely combines programmable frequency, pulse-skipping light-load operation, and auto-configurable feedback-making it optimal for space-constrained, efficiency-critical telecom and modular power designs requiring minimal external components.

Availability

MP3910GK-Z is available at Aetrix Electronics and suitable for telecom isolated power supplies, brick modules, and off-line controller designs requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for MP3910GK-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with over two decades of expertise in DC-DC conversion and power management solutions.

The MP3910 belongs to MPS's Peak Current Mode PWM Controller product line, engineered specifically for high-efficiency, multi-topology DC-DC conversion in telecom, industrial, and computing power systems where reliability and integration are critical.

FAQ

What is the minimum input voltage required for reliable startup of MP3910GK-Z?

The MP3910GK-Z requires ≥7V on VIN for guaranteed startup when VCC is unpowered. If VIN and VCC are tied together, startup is possible from 5V-but maximum input must then be limited to 13V to avoid exceeding VCC regulator limits. Below 7V, internal VCC UVLO (4.17V rising threshold) prevents enable until sufficient voltage is reached.

How does the ISENSE pin determine isolated vs. non-isolated feedback mode?

At power-up, the ISENSE pin sources a 55 µA current for 50 µs. If the resulting voltage exceeds 185 mV (e.g., with a 5–10 kΩ resistor to ground), the internal error amplifier is disabled and COMP becomes the feedback input. If voltage remains below 185 mV, the amplifier is enabled and FB is used-automatically configuring the controller without external logic.

Can MP3910GK-Z synchronize to an external clock outside its RT-set frequency range?

Yes-the EN/SYNC pin accepts external clocks from 80 kHz to 400 kHz, regardless of the RT-programmed frequency, provided the external clock is higher than the RT-set value. Clock pulses must have low-time <10 µs to avoid misinterpretation as disable signals, and voltage must stay ≤6V to prevent damage to the internal clamp zener.

What is the role of the SS pin during overvoltage or short-circuit events?

During OVP or SCP, the SS pin is discharged at 1.66 µA instead of the normal 17.8 µA (used for OLP). Once SS voltage drops to 0.2V, the controller initiates a full restart cycle-including recharging SS with 54 µA-ensuring complete reset before resuming operation, which prevents latch-up in persistent fault conditions.

Does MP3910GK-Z support boost converters with output short-circuit protection?

No-the MP3910GK-Z provides cycle-by-cycle current limiting but cannot inherently limit input-to-output current during output short in boost topology. In such cases, the controller may enter hiccup mode via SCP (at 350 mV ISENSE), but secondary protection (e.g., input fuse or eFuse) is required for safe short-circuit handling per IEC/UL standards.

What thermal derating applies to the MSOP-10 package at elevated ambient temperatures?

With θ_JA = 150°C/W on a standard 4-layer PCB, the MP3910GK-Z dissipates up to 0.83W at 25°C ambient. At 85°C ambient, maximum continuous power drops to ~0.39W ((150°C − 85°C)/150°C/W). Thermal shutdown activates at 160°C junction temperature, with 20°C hysteresis ensuring safe cooldown before restart.

How is slope compensation implemented, and is external adjustment needed?

Slope compensation is fully integrated and automatically scaled to the programmed switching frequency-no external components required. The internal ramp generator adds a sawtooth waveform proportional to F_SW to the current sense signal, preventing subharmonic oscillation in duty cycles >50%, as confirmed in the functional block diagram and oscillator section.