Monolithic Power Systems Inc. MP5013AGJ-P

Overview

MP5013AGJ-P from Monolithic Power Systems is a programmable current-limit switch with integrated 36 mΩ DMOS power FET, 5.7 V over-voltage clamp, and adjustable slew-rate control via DV/DT pin. It operates from 3 V to 5.5 V input, delivers up to 5 A trip current (adjustable via external resistor), and protects downstream circuitry in hot-swap and USB port applications.

For engineers reviewing the MP5013AGJ-P datasheet, MP5013AGJ-P pinout, MP5013AGJ-P application, or MP5013AGJ-P equivalent, this device supports precise inrush current limiting, thermal fault signaling via tri-state ENABLE/FAULT, UVLO at 2.7 V (typ), and OVP clamping - critical for robust power rail protection in storage and embedded systems.

Technical Context

The MP5013AGJ-P integrates a charge-pump–driven DMOS FET enabling low R_DS(on) (36 mΩ typ) without external gate drive. Its dual-stage current limiting distinguishes hold current (2.8 A at R_LIMIT = 22 Ω) from trip current (5 A), allowing sustained overload handling before thermal shutdown.

UVLO (2.7 V rising edge) disables output until input stabilizes; OVP clamps source voltage at 5.7 V (typ) when V_CC exceeds threshold. The ENABLE/FAULT pin provides three-level signaling: low (disable/clear fault), high (enable), mid (thermal fault latched), enabling system-level fault coordination across multiple devices.

Key Specifications

Pinout & Package

MP5013AGJ-P uses the TSOT23-8 package: 2.9 mm × 1.6 mm × 0.85 mm body, 0.65 mm lead pitch, exposed pad for thermal dissipation. Pin 1 is lower-left when top marking is read left-to-right.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar current-limit switch applications.

Compared with TPS259211DRCR and RT9711CGQW, MP5013AGJ-P uniquely combines adjustable slew rate, 5.7 V OVP clamp, and latched thermal shutdown with tri-state fault signaling - making it optimal for industrial hot-swap and mission-critical storage interfaces where deterministic fault isolation is mandatory.

Availability

MP5013AGJ-P is available at Aetrix Electronics and suitable for USB ports/hubs, hot-swap systems, storage (HDDs/SSDs), and gaming console power modules requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for MP5013AGJ-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP5013A belongs to MPS's eFuse and load switch product line, engineered specifically for robust, programmable power rail protection in high-density computing, storage, and consumer electronics where space, thermal efficiency, and fault intelligence are critical.

FAQ

What is the function of the DV/DT pin, and how does it affect startup behavior?

The DV/DT pin controls output voltage slew rate during turn-on. With no external capacitor, an internal circuit provides a fixed 1.4 ms rise time (10% to 90%). Adding capacitance extends this linearly: 1 nF yields ~31.4 ms. This prevents inrush current spikes into large output capacitors and reduces mechanical stress on connectors during hot-plug events.

How does the ENABLE/FAULT pin operate in three-level mode?

ENABLE/FAULT is a weak-pull-up (25 µA) bi-directional node. Low disables output and clears fault flag; high enables output if fault flag is clear; mid-level (0.82–1.95 V) signals latched thermal shutdown. This enables wired-OR fault buses across multiple MP5013AGJ-P devices without external logic.

Can MP5013AGJ-P be used with input voltages above 5.5 V?

No - the absolute maximum V_CC rating is 22 V, but recommended operating input is strictly 3–5.5 V. Exceeding 5.5 V violates operational specs and risks triggering OVP clamping unnecessarily. For higher-input applications, use upstream regulators or dedicated high-voltage eFuses like MP5023.

What is the difference between trip current and hold current?

At R_LIMIT = 22 Ω, trip current is 5 A - the level at which current limiting begins. Hold current is 2.8 A - the maximum sustained current the device delivers in constant-current mode before thermal shutdown. During startup, load current must stay below hold current to avoid failed turn-on.

Does MP5013AGJ-P require an external heat sink in normal operation?

No - with 36 mΩ R_DS(on), dissipating 144 mW at 5 V/2 A, and θ_JA = 100°C/W, junction temperature rise is only ~14°C above ambient. A heat sink is required only during sustained short-circuit conditions where full 5 V × 5 A = 25 W must be dissipated - exceeding the package's 1.25 W continuous rating.

How is current limit adjusted, and what resistor values correspond to common trip thresholds?

Current limit is set by resistor between I-LIMIT and SOURCE pins. At R_LIMIT = 22 Ω, trip current = 5 A; at 100 Ω, trip current = 2.7 A; at 220 Ω, trip current = 2.43 A. Hold current scales proportionally (e.g., 22 Ω → 2.8 A hold). Values are confirmed in Table 2 of the datasheet and are process-trimmed for ±15% accuracy.