Monolithic Power Systems Inc. MP5013AGJ-Z

Overview

MP5013AGJ-Z from Monolithic Power Systems is a programmable current-limit switch IC designed for input-to-output protection in 5 V power rails, featuring adjustable current limit (1–5 A), 36 mΩ integrated DMOS FET, 5.7 V over-voltage clamp, and slew-rate control via DV/DT pin. It operates across 3–5.5 V input, supports hot-swap in USB ports and SSDs, and integrates thermal shutdown, UVLO, and bi-directional ENABLE/FAULT signaling.

For engineers reviewing the MP5013AGJ-Z datasheet, MP5013AGJ-Z pinout, MP5013AGJ-Z application, or MP5013AGJ-Z equivalent, key selection criteria include programmable trip/hold current thresholds, TSOT23-8 thermal performance (θJA = 100°C/W), OVP clamping accuracy (±0.2 V), and ENABLE/FAULT three-level fault signaling behavior under thermal or UVLO events.

Technical Context

The MP5013AGJ-Z implements a sense-FET-based current-limit architecture with external resistor programming of trip (5 A typical at 22 Ω) and hold (2.8 A) thresholds. Its internal charge pump enables full enhancement of the low-RDS(on) DMOS FET, eliminating gate drive complexity.

Protection logic combines analog comparators for UVLO (2.7 V threshold, 0.13 V hysteresis), OVP (5.7 V clamp), and thermal latch (175°C shutdown). The ENABLE/FAULT pin functions as a shared bus interface with defined low/mid/high voltage states to signal enable status, thermal fault, and UVLO reset - enabling coordinated multi-device fault management in backplane systems.

Key Specifications

Pinout & Package

TSOT23-8 package: 1.6 mm × 2.9 mm footprint, 0.65 mm pitch, exposed pad for thermal dissipation. Pin 1 is lower-left when top marking "AMK" is read left-to-right.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable current-limit switch applications.

Compared with TPS25940ARVCR and AP22653AW5-7, the MP5013AGJ-Z uniquely balances analog programmability (R-set current, C-set slew), integrated 5.7 V OVP, and hardware-coordinated fault signaling - making it optimal for compact, deterministic 5 V hot-swap designs without microcontroller dependency.

Availability

MP5013AGJ-Z is available at Aetrix Electronics and suitable for USB port protection, enterprise SSD power sequencing, and hot-swap backplane modules requiring stable component supply, RoHS-compliant packaging, and guaranteed long-term lifecycle support.

Supply support for MP5013AGJ-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global distribution through authorized partners.

The MP5013A belongs to MPS's eFuse and load switch product line, engineered specifically for robust, low-footprint overcurrent and overvoltage protection in space-constrained 5 V systems such as storage, computing, and consumer electronics.

FAQ

What is the minimum recommended copper area for thermal management of MP5013AGJ-Z?

The datasheet specifies 0.5 in² (323 mm²) of 2-oz copper on the PCB for continuous 4.2 A operation at TA = 25°C. With less copper (e.g., 2.3 A at TA = 80°C), derating is required: power dissipation drops 0.1 W per 10°C ambient rise above 25°C. The exposed pad must be soldered to this thermal plane.

How does the ENABLE/FAULT pin behave during thermal shutdown?

During thermal shutdown, ENABLE/FAULT drives to an intermediate voltage level (0.82–1.95 V), distinct from low (≤0.5 V) or high (≥2.5 V). This mid-state signals thermal fault while preserving the ability to detect subsequent UVLO or external reset - and latches until VCC cycles or the pin is pulled low.

Can MP5013AGJ-Z operate with no external capacitor on the DV/DT pin?

Yes - floating DV/DT yields a default 1.4 ms output rise time (10% to 90%). This is sufficient for many USB and SSD applications. Adding capacitance (e.g., 470 pF → 15.5 ms) extends ramp time only when stricter dv/dt control is needed, such as for large bulk capacitance (>100 µF) on the load side.

What is the relationship between RLIMIT value and current limit thresholds?

RLIMIT sets both trip and hold currents: trip current ≈ 124 mV / RLIMIT (Ω), hold current ≈ 62 mV / RLIMIT (Ω). For example, 22 Ω yields ~5.6 A trip and ~2.8 A hold. Values are confirmed in Table 2 of the datasheet and vary <±10% across temperature and process.

Does MP5013AGJ-Z require an external pull-up resistor on ENABLE/FAULT?

No - the IC includes a 25 µA internal current source that pulls ENABLE/FAULT high when enabled and no fault is present. External pull-up is unnecessary and may interfere with mid-level thermal fault detection or low-level UVLO signaling.

What happens if the load draws more than the hold current during startup?

If load current exceeds the hold current (e.g., >2.8 A with 22 Ω RLIMIT) before the output fully ramps, the device enters constant-current mode and cannot reach full regulation. Startup will stall unless load capacitance is reduced or RLIMIT increased to raise the hold threshold.

Is MP5013AGJ-Z compatible with 3.3 V logic control signals?

Yes - ENABLE/FAULT interprets <0.5 V as logic low (disable), 0.82–1.95 V as mid (thermal fault), and >2.5 V as high (enable). A 3.3 V GPIO can safely drive it high; open-drain 3.3 V logic can pull it low. Do not exceed 4.95 V on ENABLE/FAULT when VCC ≤ 6 V.