Monolithic Power Systems Inc. MP5073GG-P

Overview

MP5073GG-P from Monolithic Power Systems is a 5.5V, 2A low-R_DS(ON) load switch with programmable current limit, soft-start control, output discharge, and power-good indication. It integrates a 50mΩ DMOS FET in a 2mm×2mm QFN-12 package, operates from 0.5V to 5.5V input, delivers <1µA shutdown current, and responds to short-circuit events in 200ns - used for rail sequencing and inrush control in portable SSDs and tablet power trees.

For engineers reviewing the MP5073GG-P datasheet, MP5073GG-P pinout, MP5073GG-P application, or MP5073GG-P equivalent, key selection criteria include adjustable current limit via ILIM resistor, soft-start slew rate tuning via SS capacitor, thermal shutdown at 150°C with 30°C hysteresis, and push-pull PG output with 50µs delay and 140–450mV trip threshold.

Technical Context

The MP5073GG-P uses a sense-FET topology with internal charge pump to drive the gate of a low-R_DS(ON) DMOS power switch, enabling efficient operation down to 0.5V VIN. Its current-limit magnitude is set by an external resistor on the ILIM pin, with typical limit range of 1.3–1.5A at RLIMIT = 23.8kΩ.

It implements dual-stage overcurrent protection: primary regulation (20µs response) for sustained overload and secondary fast-off (200ns) for hard short-circuit events. The PG pin provides rail-valid status with voltage-gap sensing (V_IN–V_OUT) and fixed 50µs delay before assertion.

Key Specifications

Pinout & Package

MP5073GG-P is housed in a thermally enhanced 12-pin QFN package (2mm × 2mm, 0.5mm pitch) with exposed thermal pad (pins 6, 11, and exposed pad connect to VIN). Pin functions are validated per Monolithic Power Systems Rev. 1.2 datasheet.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar load switch applications.

Compared with TPS22919DBVR and NIS5132MN3TXG, MP5073GG-P uniquely combines programmable current limit, soft-start tuning, output discharge, and push-pull PG in a 2mm×2mm footprint - making it optimal for compact, multi-rail portable systems requiring autonomous rail management.

Availability

MP5073GG-P is available at Aetrix Electronics and suitable for notebook power trees, portable SSDs, tablet SoC enable circuits, and USB-C PD sink protection requiring stable component supply, full lifecycle traceability, and volume-ready packaging.

Supply support for MP5073GG-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP5073 belongs to MPS's load switch and eFuse product line, engineered specifically for space-constrained, battery-powered devices needing precise inrush control, rail sequencing, and autonomous fault response without external components.

FAQ

What is the minimum input voltage supported by MP5073GG-P?

The MP5073GG-P operates down to 0.5V input voltage, verified per Absolute Maximum Ratings and Recommended Operating Conditions tables. This enables use with ultra-low-voltage rails such as DDR I/O supplies and sub-1V FPGA auxiliary domains, provided V_CC remains within its 3V–5.5V range.

How does the ILIM resistor affect current limit accuracy?

The ILIM resistor sets current limit using a fixed current-sense ratio (S ≈ 33,000 at VIN = V_CC = 3.6V). Accuracy depends on resistor tolerance and temperature drift; a 1% 23.8kΩ resistor yields ~1.4A ±3% typical limit. S varies slightly below 1.2V VIN or outside nominal V_CC, per datasheet curves.

Can MP5073GG-P be used without connecting the SS pin?

No - floating the SS pin or using <4.7nF capacitor causes uncontrolled output rise time limited only by MOSFET gate charge. The internal 11µA current source requires a defined external capacitor to establish predictable soft-start behavior; omission risks inrush-triggered current limiting and unstable startup.

What is the role of pins 7, 8, and 10 labeled "NC"?

Pins 7, 8, and 10 are no-connect internally but are recommended to be tied to V_OUT per the datasheet. This improves thermal performance by increasing copper area connected to the output node and ensures mechanical and thermal compatibility with pin-compatible variants MP5087 and MP5077.

Does the PG pin require an external pull-up resistor?

No - the PG pin is a push-pull output with active high and low states. It drives high to V_CC (min 3.2V at 3.3V V_CC) and sinks ≥1mA when low (max 0.3V). External pull-ups are unnecessary and may interfere with timing or logic levels.

How does thermal shutdown interact with current limiting?

During sustained overload, current limiting causes power dissipation (I²×R_DS(ON)) that raises junction temperature. At 150°C, thermal shutdown disables the FET; recovery occurs after temperature drops 30°C (to 120°C). This foldback protects against latch-up during prolonged faults without requiring manual reset.

Is the exposed thermal pad electrically connected?

Yes - the exposed pad (pins 6 and 11 plus center pad) is internally connected to VIN. It must be soldered to a large copper pour tied to the VIN net for optimal thermal performance and EMI reduction. Failure to connect it degrades θ_JA from 80°C/W to >120°C/W and risks thermal shutdown under load.