Monolithic Power Systems Inc. MP5098AGDT-Z

Overview

MP5098AGDT-Z from Monolithic Power Systems is a dual-channel e-fuse IC with integrated SAS (System Alert Signal) control, reverse current blocking for the 5V channel, and an internal 5V/10mA LDO regulator. It delivers 4.5A ±10% current limiting on the 12V channel and 3A ±10% on the 5V channel, with 44mΩ R_DS(ON) per FET, OVP thresholds of 15V (12V rail) and 5.7V (5V rail), and operates in a TQFN-10 (2mm×3mm) package for HDD/SSD power rail protection.

For engineers reviewing the MP5098AGDT-Z datasheet, MP5098AGDT-Z pinout, MP5098AGDT-Z application, or MP5098AGDT-Z equivalent, this page provides verified functional context, validated pin roles, confirmed thermal and overvoltage protection behavior, and real-world hot-swap and reverse-blocking use cases - all derived from the official MPS Rev. 1.0 datasheet.

Technical Context

The MP5098AGDT-Z implements two independent, digitally controlled e-fuse channels: Channel 1 accepts 10.8–13.2V input and delivers up to 4.5A with 15V OVP clamping; Channel 2 accepts 4.5–5.5V and delivers up to 3A with 5.7V OVP clamping. Both feature UVLO (8.6V/4.0V), fast short-circuit response (<1µs), and hiccup-mode recovery after fault.

Control logic integrates EN (global enable), SAS (system alert shutdown), and dual SS pins for independent soft-start timing via external capacitors. The 5V channel includes back-to-back N-MOSFET reverse current blocking activated within 1µs of EN/SAS deassertion, while the integrated LDO supplies 5V/10mA with ±3% regulation across load and temperature.

Key Specifications

Pinout & Package

TQFN-10 (2mm × 3mm) package with wettable flanks, MSL Level 1, 260°C reflow compatible. Exposed thermal pad requires solder connection to PCB ground plane for thermal performance (θ_JA = 40°C/W on 2-layer board).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-rail e-fuse applications.

Compared with TPS25982LARVYR and RTQ2134BGQW, MP5098AGDT-Z uniquely integrates SAS control, 5V reverse blocking, and a 5V LDO in one TQFN-10 package - reducing component count and enabling single-chip SAS-3 hot-swap compliance without external support circuitry.

Availability

MP5098AGDT-Z is available at Aetrix Electronics and suitable for hard disk drives, solid-state drives, and industrial backplane power distribution requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for MP5098AGDT-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over 20 years of expertise in DC/DC converters, e-fuses, and motor drivers.

The MP5098A belongs to MPS's SAS-compliant e-fuse product line, designed specifically for enterprise storage and industrial hot-swap applications demanding integrated protection, precise current limiting, and system-level fault signaling.

FAQ

What is the maximum absolute input voltage the MP5098AGDT-Z can withstand?

The MP5098AGDT-Z supports up to +18V on VIN1 and VIN2 under continuous operation, with transient tolerance of +22V (100ms) and –3V (1ms). These ratings are validated per Absolute Maximum Ratings table in the Rev. 1.0 datasheet and apply independently to each channel.

How does the SAS pin interact with the EN pin during normal operation?

When EN is high and SAS is pulled low for ≥100ms after VIN exceeds UVLO, both channels ramp up under controlled soft-start. If SAS is pulled low while EN is high *after* startup, it forces immediate shutdown of both channels with <1µs response - meeting SAS-3 fault signaling latency requirements.

Can the MP5098AGDT-Z be used with a 3.3V input rail?

No. The MP5098AGDT-Z is specified only for 4.5–5.5V (CH2) and 10.8–13.2V (CH1) operating ranges. Its 4V UVLO threshold and 5.7V OVP clamp are optimized for 5V systems; using 3.3V would cause UVLO lockout and prevent startup.

What is the thermal performance of the TQFN-10 package under full load?

With proper PCB layout (2-layer, 54mm×46mm, thermal pad soldered), θ_JA = 40°C/W. At 4.5A/12V (54W input), worst-case power dissipation is ~0.9W (I²R), raising junction temperature by ~36°C above ambient - well within the 125°C max operating range.

Does the integrated LDO require an external feedback resistor?

No. The 5V LDO is fully internal with fixed output; no external resistors or compensation components are needed. It delivers 4.7–5.1V across 0–10mA load and –40°C to +125°C, as verified in Electrical Characteristics Table (page 4).

How is reverse current blocking implemented on the 5V channel?

Using internal back-to-back N-channel MOSFETs between VIN2 and VOUT2, activated only when EN and SAS are both low. The device achieves <1µs turn-off delay and blocks reverse current up to the channel's current limit (3A), as confirmed in the Reverse Behavior section (page 17).

What external components are mandatory for basic operation?

Mandatory components include: two 10µF input ceramics (CIN1/CIN2), two 10µF output ceramics (COUT1/COUT2), one 1µF LDO output capacitor (COUT3), and two 100nF soft-start capacitors (CSS1/CSS2). No current-sense resistors or external FETs are required.