Monolithic Power Systems Inc. MP6400DG-01-LF-P

Overview

MP6400DG-01-LF-P from Monolithic Power Systems is a low-quiescent-current (1.6µA typ), adjustable-threshold (≥0.4V) supervisory circuit with programmable reset delay (2.1ms–10s via external capacitor), ±1% threshold accuracy, and open-drain RESET output. It monitors system supply rails in battery-powered microcontroller systems where precise power-on reset timing and ultra-low standby current are critical.

For engineers reviewing the MP6400DG-01-LF-P datasheet, MP6400DG-01-LF-P pinout, MP6400DG-01-LF-P application, or MP6400DG-01-LF-P equivalent, this device supports voltage monitoring down to 0.4V via external resistor divider, offers three CDELAY configuration modes (float/VCc/capacitor), guarantees RESET validity down to VCC = 0.8V, and operates across –40°C to +85°C in a 2mm×2mm QFN6 package.

Technical Context

The MP6400DG-01-LF-P implements a precision bandgap reference and comparator-based supervision architecture with hysteresis (1.5–3.5% of VIT) to reject SENSE pin transients up to 17.5µs. Its internal 140nA current source charges the external CDELAY capacitor to generate the user-programmable delay before de-asserting RESET after valid SENSE and MR conditions.

It features dual reset triggers: voltage drop on SENSE below factory-trimmed or resistor-divider-adjusted VIT (0.4V min), and logic-low assertion on MR (internally pulled up to VCC via 90kΩ). RESET remains asserted until both inputs exceed their thresholds *and* the CDELAY timer expires - enabling robust power sequencing in multi-rail systems.

Key Specifications

Pinout & Package

MP6400DG-01-LF-P is housed in a RoHS-compliant, thermally enhanced 2mm×2mm QFN6 package with exposed thermal pad (JEDEC MO-229 VCCC), rated for 2.5W power dissipation at TA=25°C and θJA = 50°C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory circuit applications.

Compared with MAX6326UT29D3+T and TPS3808G12DBVR, MP6400DG-01-LF-P uniquely combines sub-1V threshold adjustability, capacitor-programmable delay spanning four decades, and industry-leading 1.6µA quiescent current - making it the only option for next-gen ultra-low-power, multi-rail, and custom-voltage systems.

Availability

MP6400DG-01-LF-P is available at Aetrix Electronics and suitable for battery-powered wearables, portable medical sensors, FPGA configuration sequencing, and edge AI microcontrollers requiring stable component supply across industrial temperature ranges.

Supply support for MP6400DG-01-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-efficiency power management ICs, including DC-DC converters, LED drivers, motor drivers, and supervisory circuits.

The MP6400 product line targets ultra-low-power system supervision in space-constrained, battery-operated devices - emphasizing quiescent current optimization, flexible voltage monitoring, and robust noise immunity for mission-critical embedded applications.

FAQ

What is the minimum VCC required for MP6400DG-01-LF-P to assert a valid RESET signal?

The device guarantees RESET assertion integrity down to VCC = 0.8V, meaning it will correctly detect SENSE voltage drops and drive RESET low even as the supply collapses - critical for brown-out detection in energy-harvesting and battery-depletion scenarios.

How do I configure MP6400DG-01-LF-P to monitor a 0.85V core rail?

Connect a resistor divider (e.g., R1 = 100kΩ from 0.85V to SENSE, R2 = 10kΩ from SENSE to GND) to scale 0.85V to ~0.077V at SENSE; the internal reference adjusts VIT accordingly. Ensure divider current stays below 25nA to avoid accuracy loss.

Can the RESET output be pulled up to 5V while VCC is 1.8V?

Yes - the open-drain RESET pin supports voltages up to 6V regardless of VCC level. Use a pull-up resistor >10kΩ to 5V to ensure proper logic-high levels for 5V-tolerant MCUs without level shifters.

What capacitor value yields a 2.5s reset delay on CDELAY?

Using the formula t_D ≈ 4.99 × 10⁷ × C_DELAY (with C in farads), a 2.5s delay requires C_DELAY ≈ 50.1nF. A standard 47nF X7R ceramic capacitor achieves ~2.35s; verify with oscilloscope measurement due to ±20% capacitor tolerance.

Is the MR pin 5V-tolerant when VCC = 3.3V?

No - MR absolute maximum rating is –0.3V to VCC + 0.3V. With VCC = 3.3V, MR must stay within 0–3.6V. For 5V logic control, use a level-shifting FET (as shown in Figure 6 of the datasheet) to avoid damage.

Does MP6400DG-01-LF-P require an external reference or trimming?

No - it integrates a precision bandgap reference achieving ±1% typical VIT accuracy across temperature. No external components or calibration are needed for standard operation; resistor divider scaling preserves accuracy if divider ratio error is <0.5%.

What is the thermal performance difference between QFN6 and TSOT23-6 packages?

QFN6 (θJA = 50°C/W) dissipates 4.4× more power than TSOT23-6 (θJA = 220°C/W) at the same ambient temperature. For continuous 1.6µA operation, both packages run near ambient; however, QFN6 enables higher reliability in thermally dense layouts or under transient load conditions.