Monolithic Power Systems Inc. MP6400DG-01-LF-Z

Overview

MP6400DG-01-LF-Z from Monolithic Power Systems is a low-quiescent-current (1.6µA typ), programmable-delay supervisory circuit designed to monitor system supply voltages down to 0.4V via an external resistor divider on the SENSE pin. It features ±1% threshold accuracy, open-drain RESET output, and user-selectable reset delay from 2.1ms to 10s using an external capacitor on CDELAY - ideal for battery-powered microcontroller and FPGA power-up sequencing.

For engineers reviewing the MP6400DG-01-LF-Z datasheet, MP6400DG-01-LF-Z pinout, MP6400DG-01-LF-Z application, or MP6400DG-01-LF-Z equivalent, key selection criteria include adjustable voltage monitoring capability, guaranteed reset validity down to VCC = 0.8V, immunity to short negative SENSE transients (≤17.5µs), and compatibility with 2mm×2mm QFN6 packaging for space-constrained embedded designs.

Technical Context

The MP6400DG-01-LF-Z implements a precision voltage comparator with hysteresis (1.5–3.5% of VIT) and a programmable delay timer driven by a 140nA internal current source charging an external capacitor on CDELAY. Its SENSE input accepts voltages ≥0.4V via external divider, while MR provides manual reset control with 90kΩ internal pull-up.

RESET assertion occurs when either SENSE falls below VIT or MR drops below 0.25×VCC; de-assertion follows after the programmed delay once both inputs exceed their thresholds. The open-drain output supports rail-to-rail pull-up (up to 6V), and operation is guaranteed from VCC = 1.8V to 6V across –40°C to +85°C.

Key Specifications

Pinout & Package

MP6400DG-01-LF-Z is housed in a 2mm×2mm, 0.65mm pitch QFN6 package with exposed thermal pad. Pin 1 is marked by a dot or notch; the package is RoHS-compliant and lead-free.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory circuit applications.

Compared with MAX6326UT29D3+ and TPS3808G12DBVR, MP6400DG-01-LF-Z uniquely supports voltage monitoring down to 0.4V and fully programmable delay - critical for next-gen ultra-low-power SoCs and multi-rail FPGA platforms where flexibility outweighs fixed-function simplicity.

Availability

MP6400DG-01-LF-Z is available at Aetrix Electronics and suitable for battery-powered IoT sensor nodes, FPGA power-up sequencing, portable medical monitors, and industrial PLC I/O modules requiring stable component supply and long-term lifecycle assurance.

Supply support for MP6400DG-01-LF-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP6400 family belongs to MPS's supervisory and reset IC product line, engineered specifically for ultra-low-power, precision voltage monitoring in space- and energy-constrained embedded systems - emphasizing quiescent current optimization and flexible configuration.

FAQ

What is the minimum monitored voltage supported by MP6400DG-01-LF-Z?

The MP6400DG-01-LF-Z supports monitoring of system voltages as low as 0.4V on the SENSE pin when used with an external resistor divider. This capability is enabled by its adjustable threshold architecture - unlike fixed-threshold variants such as MP6400DG-09 (0.9V) or MP6400DG-25 (2.5V). The 0.4V lower limit is specified in the datasheet's "DESCRIPTION" section and confirmed in the "STANDARD VERSIONS" table.

How do I configure a 5-second reset delay?

To achieve a 5-second reset delay, connect a capacitor between the CDELAY pin and GND. Using the formula t_D ≈ 4.99 × 10⁻⁴ × C_DELAY (with C_DELAY in nF and t_D in seconds), a 10.02nF capacitor yields ~5s. A standard 10nF ceramic capacitor (X7R, low-leakage) is recommended and validated in the "ELECTRICAL CHARACTERISTICS" table for 102ms delay - scaling linearly confirms feasibility.

Can MP6400DG-01-LF-Z operate with VCC = 1.5V?

No - MP6400DG-01-LF-Z requires VCC ≥1.8V per the "Recommended Operating Conditions" table. Operation below 1.8V is outside specification; the absolute minimum VCC for guaranteed RESET validity is 0.8V, but functional operation (including accurate threshold detection and delay timing) is only assured from 1.8V to 6V.

Is the RESET output compatible with 5V logic systems?

Yes - the RESET pin is open-drain and rated for up to 6V on the output node. When pulled up to a 5V rail via ≥10kΩ resistor, it delivers clean logic-high signaling compatible with 5V-tolerant microcontrollers and FPGAs. This is explicitly stated in the "PIN FUNCTIONS" section and "APPLICATION INFORMATION" under "Reset Output Function".

What is the maximum allowable leakage current into the SENSE pin?

The SENSE pin leakage is ±25nA maximum at TA = +25°C for the MP6400DJ-01 variant, and the MP6400DG-01 shares identical input structure. This value is specified in the "ELECTRICAL CHARACTERISTICS" table under "Input Current at SENSE Pin". Low leakage ensures minimal error in resistor-divider-based voltage monitoring.

Does MP6400DG-01-LF-Z include hysteresis on the SENSE threshold?

Yes - the device includes built-in hysteresis of 1.5% to 3.5% of VIT, as specified in the "ELECTRICAL CHARACTERISTICS" table under "Hysteresis on VIT Pin". This prevents oscillation during slow voltage transitions near the threshold and is integral to reliable brown-out detection in noisy environments.

Can the MR pin be left unconnected?

Yes - the MR pin has an internal 90kΩ pull-up resistor to VCC, allowing it to float safely without external components. This is documented in the "PIN FUNCTIONS" description and "APPLICATION INFORMATION" section titled "Monitor Multiple System Voltages", which states "The MR is internally connected to VCC through a 90kΩ resistor so this pin can float."