Monolithic Power Systems Inc. MP6400DG-09-LF-P

Overview

MP6400DG-09-LF-P from Monolithic Power Systems is a fixed-threshold supervisory circuit with 0.84V V_IT, ±1% threshold accuracy, 1.6μA typical quiescent current, and programmable reset delay (2.1ms–10s via CDELAY pin), designed for reliable power-on reset generation in low-voltage microcontroller systems operating down to 0.8V V_CC.

For engineers reviewing the MP6400DG-09-LF-P datasheet, MP6400DG-09-LF-P pinout, MP6400DG-09-LF-P application, or MP6400DG-09-LF-P equivalent, this device delivers precision voltage monitoring, manual reset control, open-drain RESET output, and immunity to short SENSE transients - critical for battery-powered and space-constrained embedded designs.

Technical Context

The MP6400DG-09-LF-P implements a precision bandgap reference and comparator-based sensing architecture with 1.5–3.5% hysteresis to reject noise on the SENSE input. Its internal 90kΩ MR pull-up enables floating MR operation while supporting active-low manual reset assertion.

Reset assertion is triggered by either SENSE falling below 0.84V or MR pulled below 0.25×V_CC; deassertion occurs only after both inputs exceed thresholds and the CDELAY-sourced delay expires. The open-drain RESET output supports rail-to-rail pull-up (up to 6V) and remains valid down to V_CC = 0.8V.

Key Specifications

Pinout & Package

MP6400DG-09-LF-P is housed in a RoHS-compliant, lead-free 2mm × 2mm QFN-6 package with exposed thermal pad (JEDEC MO-229 VCCC), optimized for high-density PCB layouts and thermal performance (θ_JA = 50°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory circuit applications.

Compared with MAX6326UT29D3+ and TPS3808G01DBVR, MP6400DG-09-LF-P uniquely combines factory-trimmed 0.84V accuracy, sub-2μA quiescent current, and flexible delay programming in a compact QFN - making it optimal for space- and power-sensitive 0.9V system monitoring where BOM simplification matters.

Availability

MP6400DG-09-LF-P is available at Aetrix Electronics and suitable for portable medical devices, laptop power management subsystems, FPGA configuration sequencers, and battery-powered IoT edge nodes requiring stable component supply with full lifecycle traceability.

Supply support for MP6400DG-09-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers across Asia and North America and global distribution through authorized partners.

The MP6400 product line targets ultra-low-power supervisory functions in space-constrained, battery-operated, and multi-rail embedded systems - emphasizing precision thresholding, minimal quiescent consumption, and robust transient immunity.

FAQ

What is the exact V_IT threshold for MP6400DG-09-LF-P, and how is it trimmed?

The MP6400DG-09-LF-P has a factory-trimmed V_IT of 0.84V ±1% (typical) - corresponding to the 0.9V nominal supply rail. This value is laser-trimmed during wafer sort and verified per unit; no external components are required to achieve this accuracy.

Can the CDELAY pin be left unconnected, and what delay results?

Yes - leaving CDELAY floating yields a guaranteed 24ms reset delay. This is a factory-characterized fixed option, distinct from capacitor-based programming. No pull-up or pull-down is required; the pin is high-impedance in this state.

Does MP6400DG-09-LF-P support operation below 1.8V V_CC?

No - the recommended operating range starts at 1.8V. However, RESET remains valid down to V_CC = 0.8V, meaning the device will assert RESET correctly during brown-out but cannot sustain normal operation or guarantee timing specs below 1.8V.

Is an external pull-up resistor required on the RESET pin?

Yes - the RESET output is open-drain and requires an external pull-up resistor ≥10kΩ to a valid logic-high rail (up to 6V). Without it, the output cannot transition high, preventing proper microcontroller or FPGA release.

How does the MR pin behave when not actively driven?

The MR pin features an internal 90kΩ pull-up to V_CC, allowing it to float high and remain inactive. When externally pulled low (<0.25×V_CC), it forces immediate RESET assertion - enabling push-button or system-level reset coordination.

What is the maximum capacitive load allowed on the SENSE pin?

The SENSE pin supports up to 10nF of bypass capacitance for noise immunity. Larger values may slow response time and affect hysteresis effectiveness; 1nF–10nF ceramic capacitors are recommended per the datasheet for optimal transient rejection.

Does MP6400DG-09-LF-P require a minimum V_CC ramp rate for reliable power-on reset?

Yes - the device specifies a minimum V_CC rise rate of 15µs/V to ensure proper power-on reset generation. Slower ramps may cause incomplete internal initialization and unpredictable RESET timing; a 100kΩ/100nF RC filter typically satisfies this requirement.