Monolithic Power Systems Inc. MP6400DG-12-LF-P

Overview

MP6400DG-12-LF-P from Monolithic Power Systems is a fixed-threshold supervisory circuit with 1.2V sense voltage (V_IT = 1.12V), ±1% threshold accuracy, 1.6μA typical quiescent current, and programmable reset delay from 2.1ms to 10s via external capacitor on CDELAY pin. It provides open-drain RESET output and operates from 1.8V to 6V supply, supporting battery-powered microcontroller and FPGA power sequencing.

For engineers reviewing the MP6400DG-12-LF-P datasheet, MP6400DG-12-LF-P pinout, MP6400DG-12-LF-P application, or MP6400DG-12-LF-P equivalent, key selection criteria include factory-set 1.2V monitoring threshold, guaranteed reset validity down to V_CC = 0.8V, immunity to 17.5μs SENSE transients, and compatibility with TSOT23-6 and QFN6 (2mm×2mm) footprints.

Technical Context

The MP6400DG-12-LF-P implements a precision voltage monitor with internal 140nA current source charging an external capacitor on CDELAY to generate user-defined reset delays. Its comparator features 1.5–3.5% hysteresis (V_HYS) to reject noise on the SENSE input, and MR pin includes a 90kΩ internal pull-up for manual reset control without external components.

RESET assertion occurs when either SENSE falls below 1.12V or MR drops below 0.25×V_CC; deassertion requires both inputs to exceed thresholds plus full delay timing. The open-drain output supports rail-to-rail pull-up voltages up to 6V, enabling interface with higher-voltage logic domains independent of V_CC.

Key Specifications

Pinout & Package

MP6400DG-12-LF-P is housed in a RoHS-compliant 2mm×2mm 6-pin QFN package with exposed thermal pad (JEDEC MO-229 VCCC). Pin 1 is marked by a dot; the package supports reflow soldering per JEDEC J-STD-020.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory circuit applications.

Compared with TPS3808G12DBVR and MAX6326UR12+T, MP6400DG-12-LF-P offers broader delay flexibility (2.1ms–10s), lower quiescent current, QFN6 option for thermal performance, and superior SENSE transient immunity-making it optimal for battery-sensitive and noise-prone embedded systems.

Availability

MP6400DG-12-LF-P is available at Aetrix Electronics and suitable for battery-powered microcontroller systems, FPGA power sequencing, portable medical sensors, and automotive body control modules requiring stable component supply across extended temperature ranges (−40°C to +85°C).

Supply support for MP6400DG-12-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan.

The MP6400 product line delivers ultra-low-quiescent-current supervisory circuits optimized for power-constrained applications including wearables, IoT edge nodes, and automotive subsystems requiring precision voltage monitoring and configurable reset timing.

FAQ

What is the exact factory-set V_IT threshold for MP6400DG-12-LF-P?

The MP6400DG-12-LF-P has a factory-trimmed V_IT of 1.12V ±1%, corresponding to nominal 1.2V rail monitoring. This value is laser-trimmed during production and verified per datasheet Rev. 1.1, Table 1, "Standard Versions" row for MP6400DG-12.

Can MP6400DG-12-LF-P operate reliably at V_CC = 1.8V while monitoring a 1.2V rail?

Yes. The device guarantees full functionality-including RESET assertion/deassertion, 1.6μA I_CC, and ±1% V_IT accuracy-at V_CC = 1.8V. Its RESET remains valid down to V_CC = 0.8V, ensuring robust operation during brown-out conditions.

How is the 380ms reset delay configured on MP6400DG-12-LF-P?

Connect CDELAY (Pin 3) to VCC through a 50kΩ–200kΩ resistor. This configuration activates an internal circuit that sets the delay to 380ms (typical), as specified in the Electrical Characteristics table under "RESET Delay Time" with condition "CDELAY = VCC".

Does MP6400DG-12-LF-P require an external pull-up on the RESET pin?

Yes. RESET is open-drain and requires an external pull-up resistor ≥10kΩ to a voltage rail ≤6V. The datasheet specifies this in the "PIN FUNCTIONS" section and Figure 3, noting that pull-up voltage may exceed V_CC without damage.

Is the MR pin internally pulled up on MP6400DG-12-LF-P?

Yes. MR (Pin 4) includes a 90kΩ internal pull-up to VCC, allowing it to float for default high state. External drive is only needed when actively asserting reset; no external resistor is required for basic operation.

What is the maximum allowable SENSE pin voltage transient duration MP6400DG-12-LF-P can ignore?

The device rejects negative transients on SENSE up to 17.5μs when overdriven by 5% (i.e., V_SENSE = 0.95×V_IT). This value is measured per datasheet Rev. 1.1, Table 1, "SENSE Maximum Transient Duration" parameter t_w.

Which package variant does MP6400DG-12-LF-P use?

MP6400DG-12-LF-P uses the QFN6 (2mm×2mm) package with wettable flanks and exposed thermal pad, as confirmed by the "Ordering Information" table showing "MP6400DG-12" mapped to "QFN6 (2x2mm)" and top marking "AC".