Monolithic Power Systems Inc. MP6400DG-15-LF-P

Overview

MP6400DG-15-LF-P from Monolithic Power Systems is a low-quiescent-current (1.6µA typical), programmable-delay supervisory circuit with factory-set 1.5V reset threshold (±1% accuracy), 380ms fixed delay when CDELAY tied to VCC, and guaranteed RESET validity down to VCC = 0.8V. It monitors system supply rails in battery-powered microcontroller systems and portable electronics.

For engineers reviewing the MP6400DG-15-LF-P datasheet, MP6400DG-15-LF-P pinout, MP6400DG-15-LF-P application, or MP6400DG-15-LF-P equivalent, this device delivers precision voltage supervision with ultra-low power consumption, open-drain RESET output, manual reset input, and immunity to short SENSE transients - critical for reliable power-on reset in space-constrained embedded designs.

Technical Context

The MP6400DG-15-LF-P implements a precision bandgap reference and comparator-based supervision architecture with hysteresis (1.5–3.5% of VIT) to prevent chatter during voltage recovery. Its internal 90kΩ MR pull-up enables floating MR operation while supporting active-low manual reset control.

Reset assertion is triggered by either SENSE falling below 1.40V (1.5V nominal threshold) or MR pulled below 0.25×VCC; de-assertion occurs only after both inputs exceed thresholds and the programmed delay elapses. The CDELAY pin supports three configuration modes: float (24ms), VCC-connected (380ms), or capacitor-to-GND (2.1ms–10s).

Key Specifications

Pinout & Package

MP6400DG-15-LF-P is housed in a 2mm × 2mm QFN-6 package with exposed thermal pad, optimized for high-density PCB layouts and thermal performance (θJA = 50°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory circuit applications.

Compared with TPS3808G15DBVR and MAX6326LT15D3T, MP6400DG-15-LF-P uniquely combines 1.6µA IQ, 380ms factory-optimized delay, MR support, and QFN-6 thermal performance - making it optimal for compact, long-life, multi-source reset systems.

Availability

MP6400DG-15-LF-P is available at Aetrix Electronics and suitable for microcontroller power-on reset, laptop voltage monitoring, portable medical sensor nodes, and FPGA configuration supervision requiring stable component supply across industrial temperature ranges (–40°C to +85°C).

Supply support for MP6400DG-15-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP6400 product line targets ultra-low-power, precision voltage supervision for battery-critical and space-constrained embedded systems - delivering guaranteed reset behavior under brown-out, transient, and manual intervention conditions.

FAQ

What is the exact reset threshold voltage for MP6400DG-15-LF-P?

The MP6400DG-15-LF-P has a factory-set nominal reset threshold of 1.5V, with an actual trip point of 1.40V and ±1% accuracy over temperature. This value is laser-trimmed during production and does not require external resistors - confirmed in the Standard Versions table of the MP6400 Rev. 1.1 datasheet.

Can the reset delay be adjusted on MP6400DG-15-LF-P, or is it fixed?

Yes - the reset delay is configurable. While the part ships with 380ms delay enabled by tying CDELAY to VCC, it supports three modes: floating CDELAY (24ms), CDELAY-to-VCC (380ms), or CDELAY-to-GND via capacitor (2.1ms–10s). The 380ms setting is recommended for robust power-on sequencing per MPS application guidance.

Does MP6400DG-15-LF-P support manual reset functionality?

Yes - Pin 4 (MR) is a dedicated manual reset input with internal 90kΩ pull-up to VCC. Driving MR below 0.25×VCC asserts RESET immediately, independent of SENSE voltage. This allows system-level reset initiation via pushbutton, FPGA GPIO, or watchdog timeout signal.

What is the minimum supply voltage at which MP6400DG-15-LF-P guarantees valid RESET output?

The device guarantees RESET assertion remains valid down to VCC = 0.8V, as specified in the Recommended Operating Conditions table. Below this, RESET behavior is undefined - a critical feature for detecting deep brown-out conditions before processor logic becomes unreliable.

Is MP6400DG-15-LF-P compatible with 1.8V I/O systems?

Yes - its SENSE, MR, and RESET pins operate across 1.8V–6V supply range. The open-drain RESET output tolerates up to 6V, enabling direct connection to 1.8V, 3.3V, or 5V logic rails using appropriate pull-up resistors. MR logic thresholds scale with VCC (VIH = 0.7×VCC, VIL = 0.25×VCC).

What package type and thermal characteristics does MP6400DG-15-LF-P use?

It uses a 2mm × 2mm QFN-6 package with exposed thermal pad (θJA = 50°C/W on 4-layer JEDEC board). This package supports higher power dissipation (2.5W) than TSOT23-6 alternatives and improves thermal reliability in sealed enclosures or high-ambient environments.