Monolithic Power Systems Inc. MP6400DG-25-LF-P

Overview

MP6400DG-25-LF-P from Monolithic Power Systems is a fixed-threshold supervisory circuit with 2.5V SENSE voltage threshold (±1% accuracy), 1.6μA typical quiescent current, and programmable reset delay from 2.1ms to 10s via external capacitor on CDELAY pin. It features open-drain RESET output, manual reset (MR) input, and guaranteed operation down to VCC = 0.8V - designed for reliable power-on reset in battery-powered microcontroller systems.

For engineers reviewing the MP6400DG-25-LF-P datasheet, MP6400DG-25-LF-P pinout, MP6400DG-25-LF-P application, or MP6400DG-25-LF-P equivalent, key selection criteria include its factory-set 2.33V trip point (2.5V nominal), TSOT23-6/QFN6 package compatibility, low-power supervision capability, and immunity to short negative transients on the SENSE pin (up to 17.5µs at 5% overdrive).

Technical Context

The MP6400DG-25-LF-P implements a precision voltage monitor with hysteresis (1.5–3.5% of VIT) and an internal 140nA current source that charges an external capacitor on CDELAY to generate user-defined reset delays. Its SENSE input monitors system rail voltage directly, asserting open-drain RESET when falling below 2.33V (2.5V nominal) or when MR is pulled low.

It supports three delay configuration modes: floating CDELAY (24ms), CDELAY tied to VCC via 50–200kΩ resistor (380ms), or CDELAY-to-GND capacitor (2.1ms–10s). The device remains functional down to VCC = 0.8V and tolerates SENSE transients as short as 17.5µs without false triggering.

Key Specifications

Pinout & Package

MP6400DG-25-LF-P is packaged in a RoHS-compliant 2mm × 2mm QFN6 (exposed pad) with wettable flanks, optimized for automated optical inspection and thermal performance (θJA = 50°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory circuit applications.

Compared with TPS3808G33DBVR and MAX6326UT25+T, MP6400DG-25-LF-P uniquely combines 2.5V-specific accuracy, MR input for system-level reset coordination, and capacitor-programmable delay - making it optimal for flexible, low-power embedded designs requiring precise rail validation and timing control.

Availability

MP6400DG-25-LF-P is available at Aetrix Electronics and suitable for battery-powered microcontroller systems, laptop power sequencing, FPGA configuration integrity checks, and industrial handheld terminals requiring stable component supply and long-term lifecycle support.

Supply support for MP6400DG-25-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP6400 product line delivers ultra-low-power, precision voltage supervision for portable and embedded systems - engineered specifically for applications where battery life, rail accuracy, and timing flexibility are critical.

FAQ

What is the exact SENSE threshold voltage for MP6400DG-25-LF-P?

The MP6400DG-25-LF-P has a factory-trimmed SENSE threshold of 2.33V ±1% (typical) for nominal 2.5V rail monitoring. This value is laser-trimmed during production and specified over –40°C to +85°C ambient temperature, ensuring consistent trip points without external calibration components.

Can MP6400DG-25-LF-P supervise voltages lower than 2.5V?

No - MP6400DG-25-LF-P is a fixed-threshold variant set specifically for 2.5V nominal rails (2.33V actual trip point). To monitor voltages below 2.33V, use the adjustable MP6400DG-01 or MP6400DJ-01 versions, which support thresholds down to 0.4V via external resistor divider on the SENSE pin.

How do I configure a 500ms reset delay with MP6400DG-25-LF-P?

A 500ms delay is not achievable with MP6400DG-25-LF-P's standard configurations: floating CDELAY yields 24ms, tying CDELAY to VCC yields 380ms, and capacitor-based delays start at 2.1ms but require calculation. For 500ms, select the MP6400DG-30 (3.0V version) with CDELAY tied to VCC - its 380ms is closest, or add external timing logic.

Is the RESET output compatible with 5V logic systems?

Yes - the open-drain RESET output supports voltage levels up to 6V. When used with a 5V pull-up resistor, it safely interfaces with 5V-tolerant microcontrollers or FPGAs. Ensure the pull-up resistor is ≥10kΩ to maintain proper drive strength and avoid excessive leakage through the internal 140nA current source.

Does MP6400DG-25-LF-P require an external capacitor on the SENSE pin?

A 1nF–10nF bypass capacitor on SENSE is strongly recommended to improve noise immunity, especially in electrically noisy environments like motor-driven handheld devices. While not strictly required for basic functionality, omitting it increases susceptibility to false resets from fast transients or EMI coupling.

What is the maximum allowable voltage on the MR pin?

The MR pin is rated for –0.3V to +6.5V per absolute maximum ratings. However, its logic thresholds are defined relative to VCC: MR is recognized as low when ≤0.25×VCC and high when ≥0.7×VCC. Applying >6.5V risks permanent damage, and voltages outside the recommended operating range may cause undefined behavior or increased leakage.