Monolithic Power Systems Inc. MP6400DG-30-LF-P

Overview

MP6400DG-30-LF-P from Monolithic Power Systems is a low-quiescent-current (1.6µA typ), programmable-delay supervisory circuit with factory-set 3.0V reset threshold (V_IT = 2.79V), ±1% threshold accuracy, and user-selectable reset delay from 2.1ms to 10s via external capacitor on CDELAY pin. It monitors system supply rails in battery-powered microcontroller systems and asserts open-drain RESET when SENSE falls below V_IT or MR is pulled low.

For engineers reviewing the MP6400DG-30-LF-P datasheet, MP6400DG-30-LF-P pinout, MP6400DG-30-LF-P application, or MP6400DG-30-LF-P equivalent, key selection criteria include guaranteed reset validity down to V_CC = 0.8V, immunity to 17.5µs negative SENSE transients, manual reset input with 90kΩ internal pull-up, and compatibility with 1.8–6V supply range.

Technical Context

The MP6400DG-30-LF-P implements a precision voltage monitor with hysteresis (1.5–3.5% of V_IT) and dual reset triggers: SENSE voltage falling below 2.79V or MR logic-low assertion. Its internal 140nA current source charges an external capacitor on CDELAY to generate programmable delays, with reset de-assertion occurring at 1.13V capacitor voltage.

It features open-drain RESET output requiring ≥10kΩ external pull-up, supports reset assertion at V_CC as low as 0.8V, and maintains ±1% V_IT accuracy over –40°C to +85°C ambient. The device is immune to short negative transients on SENSE (≤17.5µs at 5% overdrive) and draws only 1.6µA typical supply current at 3.3V.

Key Specifications

Pinout & Package

MP6400DG-30-LF-P is housed in a 2mm × 2mm QFN-6 package with exposed thermal pad, optimized for space-constrained portable designs and offering 50°C/W junction-to-ambient thermal resistance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory circuit applications.

Compared with TPS3808G33DBVR and MAX6326UT33+T, MP6400DG-30-LF-P offers tighter ±1% threshold accuracy, lower 1.6µA quiescent current, and capacitor-based delay tuning-critical for battery longevity and flexible power sequencing in portable medical and IoT devices.

Availability

MP6400DG-30-LF-P is available at Aetrix Electronics and suitable for battery-powered IoT sensor nodes, FPGA configuration sequencing, and portable medical diagnostic devices requiring stable component supply and long-term lifecycle support.

Supply support for MP6400DG-30-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan.

The MP6400 product line delivers ultra-low-power, precision supervisory circuits for battery-critical and noise-prone embedded systems-designed specifically for reliable reset generation in portable, medical, and industrial edge devices.

FAQ

What is the exact reset threshold voltage for MP6400DG-30-LF-P?

The MP6400DG-30-LF-P has a factory-set nominal reset threshold of 3.0V, with a specified V_IT of 2.79V and ±1% accuracy over temperature. This value is laser-trimmed during production and does not require external resistor dividers, unlike the adjustable MP6400DG-01 variant.

Can MP6400DG-30-LF-P operate reliably at V_CC = 1.8V?

Yes-MP6400DG-30-LF-P is fully specified from 1.8V to 6V supply voltage. At 1.8V, it guarantees RESET assertion when SENSE drops below 2.79V (with V_CC ≥ 0.8V), and maintains ±1% threshold accuracy and 1.6µA typical quiescent current per datasheet Section 4.

How do I configure a 500ms reset delay using the CDELAY pin?

To achieve ~500ms delay, connect a 4.7nF ceramic capacitor between CDELAY and GND. Per the delay equation t_D ≈ (C_DELAY × 10⁻⁹) × 4.99 × 10⁶ s/nF, this yields 4.7 × 4.99 ≈ 23.4ms-so instead use the V_CC-tie method: connect CDELAY to V_CC through a 100kΩ resistor, which selects the guaranteed 380ms delay mode per datasheet Table 1.

Is the RESET output compatible with 5V logic systems?

Yes-the open-drain RESET output supports voltage levels up to 6V when pulled up externally, making it interoperable with 5V microcontrollers and FPGAs. The datasheet explicitly permits pull-up to supplies higher than V_CC, and leakage is limited to 300nA at 6V.

Does MP6400DG-30-LF-P require an external pull-up resistor on the RESET pin?

Yes-a minimum 10kΩ external pull-up resistor is required on the open-drain RESET pin to ensure proper logic-high state when de-asserted. The datasheet specifies this value to guarantee sufficient rise time and noise margin, especially when interfacing with high-capacitance MCU reset inputs.

What is the maximum allowable negative transient on the SENSE pin?

The SENSE pin tolerates negative transients up to 17.5µs duration when the overdrive is 5% (i.e., V_SENSE = 0.95 × V_IT). This immunity is measured under specified test conditions and ensures robust operation during switching regulator cross-talk or ESD events near power rails.

How does the MR pin behave when left unconnected?

When MR is left floating, its internal 90kΩ pull-up resistor biases it to V_CC, keeping the pin at logic high and preventing spurious reset assertion. This allows MR to be omitted in designs where only SENSE monitoring is needed, reducing BOM count and layout complexity.