Monolithic Power Systems Inc. MP6400DG-33-LF-P

Overview

MP6400DG-33-LF-P from Monolithic Power Systems is a fixed-threshold supervisory circuit with 3.3V nominal sense voltage (V_IT = 3.07V), ±1% threshold accuracy, 1.6µA typical quiescent current, and programmable reset delay from 2.1ms to 10s via external capacitor on CDELAY pin. It operates from 1.8V to 6V supply and asserts open-drain RESET when SENSE falls below V_IT or MR is pulled low - used for reliable power-on reset in battery-powered microcontroller systems.

For engineers reviewing the MP6400DG-33-LF-P datasheet, MP6400DG-33-LF-P pinout, MP6400DG-33-LF-P application, or MP6400DG-33-LF-P equivalent, this device delivers precision voltage monitoring with ultra-low ICC, guaranteed RESET validity down to V_CC = 0.8V, immunity to short negative SENSE transients (<17.5µs), and flexible delay configuration via CDELAY pin states (float, V_CC-tied, or capacitor-coupled).

Technical Context

The MP6400DG-33-LF-P implements a precision bandgap reference and comparator-based sensing architecture with internal 90kΩ MR pull-up, enabling dual-trigger reset assertion (SENSE undervoltage or MR logic-low). Its reset delay is generated by charging an external capacitor at 140nA until reaching 1.13V threshold - supporting deterministic timing across temperature and supply.

It features hysteresis (1.5–3.5% of V_IT) to prevent chatter during threshold crossing, open-drain RESET output rated for 5mA sink and compatible with voltages up to 6V, and guaranteed operation down to V_CC = 0.8V - ensuring valid reset assertion even during brown-out conditions before full system startup.

Key Specifications

Pinout & Package

MP6400DG-33-LF-P is housed in a RoHS-compliant, lead-free 2mm × 2mm QFN-6 package with exposed thermal pad (JEDEC MO-229 VCCC), optimized for high-density PCB layouts and thermal performance (θ_JA = 50°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory circuit applications.

Compared with TPS3808G33DBVR and MAX6326UT33+T, MP6400DG-33-LF-P uniquely combines MR input, capacitor-programmable delay, and open-drain RESET with higher voltage tolerance - making it optimal for flexible, low-power, multi-trigger reset architectures.

Availability

MP6400DG-33-LF-P is available at Aetrix Electronics and suitable for battery-powered microcontrollers, laptop power sequencing, FPGA configuration integrity, and industrial PLC I/O modules requiring stable component supply with full lifecycle support.

Supply support for MP6400DG-33-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP6400 product line delivers ultra-low-power, precision voltage supervision for portable and energy-constrained systems - targeting applications where long battery life, accurate reset thresholds, and flexible delay timing are critical.

FAQ

What is the exact V_IT threshold for MP6400DG-33-LF-P?

The MP6400DG-33-LF-P has a factory-trimmed V_IT of 3.07V with ±1% accuracy over –40°C to +85°C ambient temperature. This value is specified in the Standard Versions table of the datasheet and confirmed by electrical characterization at 25°C and across temperature extremes.

Can MP6400DG-33-LF-P monitor voltages other than 3.3V?

No - MP6400DG-33-LF-P is a fixed-threshold variant calibrated specifically for 3.3V rail supervision (V_IT = 3.07V). For adjustable monitoring down to 0.4V, use MP6400DG-01 or MP6400DJ-01, which accept external resistor dividers on the SENSE pin.

How do I configure a 500ms reset delay?

A 500ms delay is not directly supported by the standard configurations (24ms float, 380ms V_CC-tied), but can be achieved using a capacitor on CDELAY. Per the datasheet equation, a ~22nF capacitor yields ~500ms delay. Use a low-leakage ceramic capacitor and minimize stray capacitance for accuracy.

Is the RESET output compatible with 5V logic systems?

Yes - the open-drain RESET output supports pull-up to any voltage up to 6V, including 5V logic rails. The datasheet specifies absolute maximum rating of 6V on RESET and guarantees proper operation when pulled up to 5V with ≥10kΩ resistor.

Does MP6400DG-33-LF-P require an external pull-up on MR?

No - MR has an internal 90kΩ pull-up to V_CC, allowing direct connection of a momentary switch to GND without external components. This simplifies manual reset implementation and reduces bill-of-materials count.

What is the minimum V_CC required for valid RESET assertion?

The device guarantees valid RESET assertion down to V_CC = 0.8V, as stated in the Recommended Operating Conditions table. Below this voltage, RESET behavior is undefined - but this threshold ensures robust reset generation during brown-out events before full system power collapse.

How does the SENSE pin handle noise in high-EMI environments?

The SENSE pin includes built-in hysteresis (1.5–3.5% of V_IT) and supports external 1nF–10nF bypass capacitors. Combined with 17.5µs transient immunity at 5% overdrive, this provides robust rejection of switching noise and ESD-induced spikes without requiring additional filtering circuitry.