Monolithic Power Systems Inc. MP6400DJ-01-LF-P

Overview

MP6400DJ-01-LF-P from Monolithic Power Systems is a low-quiescent-current (1.6 µA typ), programmable-delay supervisory circuit in TSOT23-6 package, monitoring system voltages down to 0.4 V with ±1% threshold accuracy and user-selectable reset delay from 2.1 ms to 10 s via external capacitor on CDELAY pin. It delivers open-drain RESET output and supports manual reset (MR) input for embedded microcontroller power-up sequencing in battery-powered portable devices.

For engineers reviewing the MP6400DJ-01-LF-P datasheet, MP6400DJ-01-LF-P pinout, MP6400DJ-01-LF-P application, or MP6400DJ-01-LF-P equivalent, key selection criteria include adjustable SENSE threshold via resistor divider, guaranteed RESET validity down to VCC = 0.8 V, immunity to 17.5 µs negative SENSE transients, and compatibility with 1.8–6 V supply rails.

Technical Context

The MP6400DJ-01-LF-P implements a precision voltage monitor with internal 140 nA current source charging an external capacitor on CDELAY to generate programmable reset delay. Its SENSE input accepts user-defined thresholds ≥0.4 V via external resistor divider, while MR provides asynchronous reset control with internal 90 kΩ pull-up.

It features open-drain RESET output requiring external pull-up >10 kΩ, operates across –40°C to +85°C, and maintains functional reset assertion down to VCC = 0.8 V - enabling reliable brown-out detection during deep low-voltage discharge in portable systems.

Key Specifications

Pinout & Package

MP6400DJ-01-LF-P is housed in a 6-pin TSOT23 package (2.9 mm × 1.6 mm × 1.0 mm height), optimized for space-constrained portable designs. The package includes exposed pad for thermal dissipation and supports standard reflow profiles.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory circuit applications.

Compared with TPS3808G01DBVR and MAX6326UT29D3+, MP6400DJ-01-LF-P uniquely combines adjustable SENSE threshold, MR input, and ultra-low ICC in TSOT23-6 - making it optimal for multi-rail, manually controllable, and battery-sensitive designs.

Availability

MP6400DJ-01-LF-P is available at Aetrix Electronics and suitable for portable medical sensors, wearable fitness trackers, FPGA configuration sequencing, and smart home edge nodes requiring stable component supply with full RoHS compliance and traceable sourcing.

Supply support for MP6400DJ-01-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and mixed-signal ICs for power management, motor drive, and sensing applications.

The MP6400 product line delivers ultra-low-power, precision supervisory circuits targeting battery-operated and space-constrained embedded systems where reliability, accuracy, and design flexibility are critical.

FAQ

What is the minimum VCC required for MP6400DJ-01-LF-P to assert a valid RESET?

The device guarantees RESET assertion down to VCC = 0.8 V, ensuring fail-safe operation during deep battery discharge. Below this voltage, RESET behavior is undefined - consistent with most microcontrollers ceasing operation at sub-0.8 V, so no functional conflict arises in system-level reset sequencing.

Can the SENSE pin monitor voltages above 6 V?

No - absolute maximum SENSE voltage is 6 V. To monitor higher rails (e.g., 12 V), an external resistor divider must scale the input to ≤6 V while maintaining SENSE pin leakage (±25 nA) and noise immunity. The divider's Thevenin resistance should remain <100 kΩ to avoid threshold error from input bias current.

How does the CDELAY pin achieve three distinct delay modes?

CDELAY supports three configurations: (1) floating → 24 ms internal timer; (2) tied to VCC via 50–200 kΩ resistor → 380 ms; (3) capacitor to GND (≥150 pF) → programmable 2.1 ms–10 s delay. Each mode uses different internal current sources and comparators - no external components needed beyond the capacitor or resistor.

Is the RESET output compatible with 5 V logic systems when VCC = 3.3 V?

Yes - the open-drain RESET output tolerates up to 6 V on the line, allowing direct connection to 5 V pull-up resistors. This enables interoperability with legacy 5 V peripherals while powered from 3.3 V, eliminating level shifters in mixed-voltage designs.

What is the impact of stray capacitance on CDELAY timing accuracy?

Stray capacitance at CDELAY adds directly to the timing capacitor value, causing longer-than-expected delays. Layout best practices include minimizing trace length, avoiding adjacent signal routing, and using guard rings. For 1% timing accuracy, stray capacitance should be <1% of the selected CDELAY value (e.g., <1.5 pF for 150 pF nominal).

Does the MR pin require an external pull-down to ensure clean release?

No - MR has an internal 90 kΩ pull-up to VCC, so it floats high by default. An external pull-down is only needed if active-low logic must override the internal pull-up (e.g., pushbutton reset). In such cases, a 10 kΩ pull-down ensures MR reaches ≤0.25×VCC reliably while limiting current to ~33 µA at 3.3 V.