Monolithic Power Systems Inc. MP6400DJ-09-LF-P

Overview

MP6400DJ-09-LF-P from Monolithic Power Systems is a fixed-threshold supervisory circuit with 0.84V sense voltage threshold, 1.6μA typical quiescent current, ±1% threshold accuracy, and programmable reset delay (2.1ms–10s via CDELAY pin), designed to monitor 0.9V system rails in battery-powered microcontroller systems.

For engineers reviewing the MP6400DJ-09-LF-P datasheet, MP6400DJ-09-LF-P pinout, MP6400DJ-09-LF-P application, or MP6400DJ-09-LF-P equivalent, key selection criteria include guaranteed reset validity down to VCC = 0.8V, open-drain RESET output compatibility with 6V-tolerant microprocessor inputs, immunity to ≤17.5μs SENSE transients, and TSOT23-6 package suitability for space-constrained portable designs.

Technical Context

The MP6400DJ-09-LF-P implements a precision voltage comparator with hysteresis (1.5–3.5% of VIT) and an internal 140nA current source that charges an external capacitor on the CDELAY pin to generate user-programmable reset delays. It features dual reset triggers: SENSE voltage falling below 0.84V or MR pulled low.

Its open-drain RESET output requires an external pull-up resistor (>10kΩ) and supports voltage levels up to 6V-exceeding VCC-enabling interface with higher-voltage logic domains. The device remains functional across VCC = 1.8V to 6V and guarantees valid reset assertion down to VCC = 0.8V during power-down sequences.

Key Specifications

Pinout & Package

MP6400DJ-09-LF-P is housed in a 6-pin TSOT23 package (2.9mm × 1.6mm × 1.0mm height), optimized for high-density PCB layouts in portable electronics. The package features gull-wing leads, RoHS-compliant matte tin plating, and JEDEC MO-193 AB compliance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory circuit applications.

Compared with MAX6326–UR29 and TPS3808G01DBVR, MP6400DJ-09-LF-P uniquely combines 0.84V fixed threshold, 1.6μA ICC, and three-mode delay configuration in TSOT23-6-making it optimal for cost-sensitive, space-constrained 0.9V rail supervision where simplicity and ultra-low power are primary.

Availability

MP6400DJ-09-LF-P is available at Aetrix Electronics and suitable for portable medical sensors, wireless edge nodes, FPGA configuration monitoring, and automotive infotainment subsystems requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for MP6400DJ-09-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP6400 family was developed specifically for ultra-low-power supervisory functions in battery-operated and energy-harvesting systems, emphasizing precision threshold accuracy, nanoscale quiescent current, and flexible reset timing without external active components.

FAQ

What is the exact reset threshold voltage for MP6400DJ-09-LF-P?

The MP6400DJ-09-LF-P has a factory-set VIT of 0.84V with ±1% accuracy over –40°C to +85°C. This is trimmed to monitor a nominal 0.9V supply rail, providing a 60mV undervoltage margin before reset assertion.

Can the CDELAY pin be left unconnected for a default delay?

Yes-leaving CDELAY floating configures a fixed 24ms reset delay. This is a defined operating mode per the datasheet and requires no external components, making it ideal for rapid prototyping or applications with tight boot timing.

Is an external pull-up resistor required on the RESET pin?

Yes-an external pull-up resistor (>10kΩ) is mandatory because RESET is open-drain. The resistor connects between RESET and the target microprocessor's supply rail (up to 6V), enabling logic-high signaling when not asserted.

Does MP6400DJ-09-LF-P support monitoring voltages below 0.9V?

No-it is a fixed-threshold variant set to 0.84V for 0.9V rail supervision. For sub-0.9V monitoring (e.g., 0.6V core supplies), the MP6400DJ-01 adjustable version with external resistor divider must be used.

What is the minimum VCC required for guaranteed RESET functionality?

The device guarantees valid RESET assertion down to VCC = 0.8V, as specified in the Absolute Maximum Ratings table. Below this, RESET behavior is undefined-ensuring fail-safe operation during deep brown-out conditions.

How does the MR pin behave when left unconnected?

MR is internally pulled up to VCC via a 90kΩ resistor, so it defaults to logic high when floating. Driving MR low (≤0.25×VCC) forces immediate RESET assertion regardless of SENSE voltage-useful for software-triggered resets or system-level fault recovery.

What capacitor value yields a 100ms reset delay?

A 1.5nF capacitor from CDELAY to GND produces approximately 100ms delay, calculated using the formula td ≈ 4.99 × 10⁷ × CDELAY (in farads). Ceramic capacitors with low leakage (e.g., X7R, C0G) are strongly recommended for timing accuracy.