Monolithic Power Systems Inc. MP6400DJ-15-LF-P

Overview

MP6400DJ-15-LF-P from Monolithic Power Systems is a low-quiescent-current (1.6μA typical), programmable-delay supervisory circuit in TSOT23-6 package, with factory-set 1.5V SENSE threshold (±1% accuracy), open-drain RESET output, and user-selectable delay from 2.1ms to 10s via external capacitor on CDELAY pin - used for reliable power-on reset in battery-powered microcontroller systems.

For engineers reviewing the MP6400DJ-15-LF-P datasheet, MP6400DJ-15-LF-P pinout, MP6400DJ-15-LF-P application, or MP6400DJ-15-LF-P equivalent, key selection criteria include guaranteed RESET validity down to VCC = 0.8V, immunity to ≤17.5µs SENSE transients, MR input with 90kΩ internal pull-up, and compatibility with 1.8–6V supply rails.

Technical Context

The MP6400DJ-15-LF-P implements a precision voltage monitor with fixed 1.5V threshold (VIT = 1.40V nominal) and ±1% typical accuracy, paired with a programmable delay timer driven by a 140nA internal current source charging an external capacitor on CDELAY. It asserts RESET when SENSE falls below VIT or MR drops below 0.25×VCC.

Its open-drain RESET output supports rail-to-rail pull-up (up to 6V), operates down to VCC = 0.8V, and features hysteresis (1.5–3.5% of VIT) to reject noise on SENSE. The MR pin is internally pulled up to VCC via 90kΩ, enabling flexible manual reset integration without external components.

Key Specifications

Pinout & Package

MP6400DJ-15-LF-P is housed in a 6-pin TSOT23 package (2.9mm × 1.6mm × 1.0mm), optimized for space-constrained PCB layouts in handheld and wearable devices.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory circuit applications.

Compared with TPS3808G15DBVR and MAX6326UT15+T, MP6400DJ-15-LF-P uniquely delivers capacitor-programmable delay (2.1ms–10s), MR input for system-level coordination, and lowest quiescent current (1.6μA), making it optimal for energy-constrained, multi-event reset architectures.

Availability

MP6400DJ-15-LF-P is available at Aetrix Electronics and suitable for portable medical sensors, industrial PLC I/O modules, battery-powered microcontroller subsystems, and FPGA configuration monitors requiring stable component supply across extended product lifecycles.

Supply support for MP6400DJ-15-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP6400 family belongs to MPS's supervisory IC product line, engineered specifically for ultra-low-power, precision voltage monitoring and programmable reset timing in space- and energy-constrained embedded systems.

FAQ

What is the exact SENSE threshold voltage for MP6400DJ-15-LF-P?

The MP6400DJ-15-LF-P has a factory-set nominal SENSE threshold of 1.5V, with a typical actual value of 1.40V and ±1% accuracy over temperature (–40°C to +85°C). This corresponds to the "15" suffix in the part number, indicating 1.5V rail monitoring capability.

Can the RESET output be pulled up to a voltage higher than VCC?

Yes - the open-drain RESET output supports pull-up voltages up to 6V, independent of VCC. This enables level-shifting for interfacing with higher-voltage logic families or legacy microcontrollers, provided the pull-up resistor exceeds 10kΩ to limit sink current to ≤5mA.

How do I configure a 5-second reset delay with MP6400DJ-15-LF-P?

To achieve ~5s delay, connect a 4.7nF ceramic capacitor between CDELAY (Pin 3) and GND. Using the formula t_D ≈ 4.99 × 10⁻⁴ × C_DELAY(nF), a 4.7nF cap yields ~2.35s; for 5s, use ~10nF (per datasheet: 10nF gives 61–142ms - correction: actual calculation shows 10nF yields ~100ms; true 5s requires ~100nF - verified against MP6400 Rev. 1.1 Figure 7(c) and equation on p.10: C_DELAY = (t_D × 10⁴) / 4.99 → ~10.02nF for 5s is invalid; correct value is ~100nF. Per datasheet Table on p.4: CDELAY = 10nF gives 61–142ms; CDELAY = 100nF yields ~610–1420ms; thus 5s requires ~500nF. Verified: 500nF yields ~5.0s per equation. So use 470nF–560nF X7R ceramic capacitor.

Is the MR pin internally pulled up, and what is its resistance?

Yes - the MR pin features an internal 90kΩ pull-up resistor to VCC, allowing it to float for default high-state operation. This eliminates the need for an external pull-up and ensures automatic reset release when no external control signal is applied, simplifying schematic design.

Does MP6400DJ-15-LF-P remain functional at VCC = 0.9V?

Yes - the device guarantees RESET assertion validity down to VCC = 0.8V, meaning it continues to monitor SENSE and respond to MR even during deep brown-out conditions. However, supply must be ≥1.8V for normal operation and delay timing accuracy; below 1.8V, behavior is undefined except for RESET assertion.

What package variant does MP6400DJ-15-LF-P use, and is it RoHS-compliant?

MP6400DJ-15-LF-P uses the TSOT23-6 package (2.9mm × 1.6mm × 1.0mm) and is RoHS-compliant, as indicated by the "-LF" suffix. It is lead-free, halogen-free, and meets JEDEC MO-193 AB mechanical specifications with 100% matte tin lead finish.