Monolithic Power Systems Inc. MP6401DJ-25AD3-LF-Z

Overview

MP6401DJ-25AD3-LF-Z from Monolithic Power Systems is a 300mA low-dropout linear regulator with integrated push-pull active-low reset circuit, delivering 2.5V ±2% output voltage from 2.5V–5.5V input. It features 114mV dropout at full load, 80μA quiescent current, and 200ms reset delay with –7.5% output threshold. Used in portable GPS and smart phone power rails for microprocessor supply monitoring and brownout recovery.

For engineers reviewing the MP6401DJ-25AD3-LF-Z datasheet, MP6401DJ-25AD3-LF-Z pinout, MP6401DJ-25AD3-LF-Z application, or MP6401DJ-25AD3-LF-Z equivalent, key selection criteria include fixed 2.5V output accuracy, TSOT23-6 package footprint, integrated reset timing (200ms), reverse leakage protection (<1μA), and thermal shutdown at 150°C.

Technical Context

The MP6401DJ-25AD3-LF-Z integrates a precision LDO regulator core with an independent reset comparator that monitors VOUT against a –7.5% threshold relative to nominal 2.5V output. Its EN pin enables high-side logic control, while ADJ tied to GND selects fixed 2.5V mode per internal resistor divider.

Reset assertion occurs within 30μs of VOUT falling below 2.3125V (92.5% of 2.5V), followed by a guaranteed 200ms delay before deassertion upon recovery. The device uses a PMOS pass element with reverse current blocking and thermal foldback limiting peak junction temperature to 150°C.

Key Specifications

Pinout & Package

MP6401DJ-25AD3-LF-Z is housed in a 6-pin TSOT23-6 package (2.9mm × 1.6mm × 1.0mm height) with exposed thermal pad. Pin 1 is marked by a dot; pin numbering follows JEDEC MO-193 AB standard with pin 1 at lower-left when top marking is read left-to-right.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO-with-reset applications.

Compared with TPS74201DRCT and MCP1825-2502E/DB, MP6401DJ-25AD3-LF-Z uniquely integrates push-pull RESET with factory-programmed 200ms delay and –7.5% threshold in TSOT23-6, eliminating external components while supporting battery-backed SRAM retention via sub-1μA reverse leakage.

Availability

MP6401DJ-25AD3-LF-Z is available at Aetrix Electronics and suitable for smartphone baseband power, portable GPS receivers, and wireless audio transmitters requiring stable component supply with controlled reset timing and low-noise regulation.

Supply support for MP6401DJ-25AD3-LF-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and mixed-signal ICs for power management, motion control, and automotive applications.

The MP6401 product line delivers integrated LDO + reset solutions targeting space-constrained portable electronics, emphasizing ultra-low IQ, precise voltage accuracy, and robust fault protection for battery-powered systems.

FAQ

What is the function of the ADJ pin on MP6401DJ-25AD3-LF-Z?

The ADJ pin selects operating mode: when tied to GND, it configures the device for fixed 2.5V output; leaving it open or floating disables regulation and must be avoided. Unlike adjustable variants, this part does not support external resistor programming-the ADJ pin serves solely as a mode enable for the factory-trimmed 2.5V output.

Can MP6401DJ-25AD3-LF-Z operate with a 2.4V input supply?

No. The absolute minimum input voltage is 2.5V per datasheet specifications, and the undervoltage lockout (UVLO) activates below 2.05V typical. At 2.4V input, the device will not regulate-output collapses and RESET asserts. For sub-2.5V operation, a different LDO such as MP2017 (1.8V–5.5V input) is required.

Does the RESET output require an external pull-up resistor?

No. MP6401DJ-25AD3-LF-Z features a push-pull RESET output capable of both sinking and sourcing current. It actively drives low (≤0.4V at 3.2mA) when asserted and high (≥0.8×VOUT) when deasserted, eliminating the need for external pull-up components and reducing layout complexity.

What is the maximum allowable power dissipation for MP6401DJ-25AD3-LF-Z in TSOT23-6?

At TA = +25°C, the TSOT23-6 package has θJA = 220°C/W, yielding a maximum continuous power dissipation of 570mW (PD(MAX) = (150°C − 25°C)/220°C/W). Derating is required above +25°C ambient; at +70°C, max PD drops to 364mW to maintain TJ ≤ 150°C.

How does the reverse current protection behave during battery backup operation?

When main input (IN) is removed while backup voltage remains on OUT, the internal MOSFET blocks reverse current flow. Measured reverse leakage is <1μA, enabling multi-day SRAM retention using a 220mAh coin cell. RESET asserts immediately upon IN removal, signaling the host to enter backup mode before VOUT decays below 2.3125V.

Is the 200ms reset delay time programmable or fixed for this variant?

The 200ms delay is factory-programmed and fixed for MP6401DJ-25AD3-LF-Z, corresponding to the "D3" suffix in the part number. No external components or pins adjust this timing-it is trimmed during wafer test and cannot be modified in-circuit. Alternate delays (3.125ms, 25ms, 1580ms) require different part numbers.

What output capacitor is recommended for stable operation?

A minimum 3.3μF X7R or X5R ceramic capacitor is required on the OUT pin, placed within 3mm of the device. For improved transient response and PSRR, a 10μF capacitor is recommended. ESR must remain below 100mΩ; tantalum or aluminum electrolytics are not supported due to instability risk.