Monolithic Power Systems Inc. MP6402DN-EF-LF-Z

Overview

MP6402DN-EF-LF-Z from Monolithic Power Systems is a dual-channel, high-PSRR linear regulator with integrated reset circuitry, delivering 500mA per channel at ±1.5% output voltage accuracy (0.9V–3.3V), 60dB PSRR at 100Hz, and programmable reset delay via external capacitor. It operates from 2.5V–5.5V input, supports -40°C to +125°C junction temperature, and is used in portable GPS and wireless devices requiring stable dual-rail power with system-level reset supervision.

For engineers reviewing the MP6402DN-EF-LF-Z datasheet, MP6402DN-EF-LF-Z pinout, MP6402DN-EF-LF-Z application, or MP6402DN-EF-LF-Z equivalent, this page provides verified technical context, package-specific pin functions, real-world use cases, and validated alternative options for dual LDO + reset IC selection in space-constrained consumer and portable electronics designs.

Technical Context

The MP6402 integrates two independent P-channel MOSFET-based LDOs with separate current limiting and thermal shutdown circuits. Each channel delivers up to 500mA with dropout voltage as low as 260mV at full load and 15µVRMS output noise over 100Hz–80kHz.

Its dedicated reset function monitors only OUT2 voltage, asserting an open-drain active-low RESET signal when VOUT2 falls below 92.5% of nominal, with delay time set by an external capacitor on ExtCap (e.g., 2.1ms with 3300pF). EN enables/disables both regulators simultaneously with logic-level control.

Key Specifications

Pinout & Package

MP6402DN-EF-LF-Z uses the SOIC8E package (exposed pad), offering enhanced thermal performance (θJA = 55°C/W) and mechanical robustness for industrial-grade mounting. Pin numbering follows standard JEDEC MS-012 BA variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual LDO with reset applications.

Compared with XC6223D182MR-G and RT9013-18PB, MP6402DN-EF-LF-Z uniquely delivers dual 500mA LDOs with OUT2-monitored reset and user-programmable delay - essential for coordinated power sequencing in multi-rail portable electronics where space and component count are constrained.

Availability

MP6402DN-EF-LF-Z is available at Aetrix Electronics and suitable for portable GPS devices, wireless audio transceivers, and Blu-ray player logic boards requiring stable component supply, RoHS-compliant packaging, and guaranteed long-term availability.

Supply support for MP6402DN-EF-LF-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan.

The MP6402 belongs to MPS's dual LDO with integrated supervisory function product line, engineered specifically for space-constrained portable electronics needing coordinated dual-rail regulation and deterministic system reset behavior.

FAQ

What is the maximum allowable input voltage for MP6402DN-EF-LF-Z?

The absolute maximum input voltage is 6V, but the recommended operating range is 2.5V to 5.5V. Exceeding 6V risks permanent damage to internal pass transistors and protection circuitry, as specified in the Absolute Maximum Ratings table. Operation above 5.5V voids parametric guarantees including PSRR, dropout, and reset accuracy.

Can OUT1 and OUT2 be set to the same voltage?

Yes, but only for specific factory-configured versions - Table 1 lists codes D (1.3V/1.3V), E (1.8V/1.8V), F (2.5V/2.5V), and G (2.8V/2.8V). The MP6402DN-EF-LF-Z top marking "6402DNEF" corresponds to code E, delivering 1.8V on both outputs with ±1.5% accuracy. Non-standard combinations require custom ordering with MOQ of 25,000 units.

How does the RESET pin behave during thermal shutdown?

RESET becomes active (low) during thermal shutdown, regardless of OUT2 voltage level. This ensures system-level reset is asserted when junction temperature exceeds 150°C, providing fail-safe behavior for overheating conditions. RESET remains active until both thermal recovery (TJ ≤ 130°C) and OUT2 voltage restoration occur, followed by the programmed delay.

Is the EN pin 5V-tolerant when powered from a 3.3V supply?

No. EN logic thresholds are ratiometric: VIH = 0.7 × VIN and VIL = 0.3 × VIN. With VIN = 3.3V, VIH ≈ 2.31V and VIL ≈ 0.99V. Applying 5V to EN violates Absolute Maximum Rating (-0.3V to +6V) only at DC, but sustained 5V may accelerate gate oxide degradation. Use a level-shifter or resistor divider for safe interfacing with 5V controllers.

What is the minimum recommended output capacitor ESR?

The MP6402 is optimized for ceramic capacitors with ESR < 0.5Ω. No minimum ESR is required - unlike older LDOs, it remains stable with near-zero-ESR ceramics (e.g., X7R, X5R). Using higher-ESR tantalum or aluminum electrolytics may cause instability or degraded transient response, as confirmed in the Output Capacitor Selection section.

Does the output discharge feature activate during EN-driven shutdown?

Yes. Output discharge engages whenever the device is disabled - whether by pulling EN low or by thermal shutdown or overcurrent fault. The 100Ω internal discharge path connects each OUT pin to GND, discharging external capacitors within milliseconds. This prevents back-powering of upstream circuitry and ensures predictable power-down sequencing.

Can RESET be used without an external pull-up resistor?

No. RESET is an open-drain output and requires an external pull-up resistor to a valid supply rail (typically VOUT2 or system VCC). Omitting the pull-up results in undefined logic state and failed reset signaling. The datasheet specifies R1 > 10kΩ; values between 10kΩ and 100kΩ balance speed, power, and noise immunity.