Monolithic Power Systems Inc. MP6402DN-LF-P

Overview

MP6402DN-LF-P from Monolithic Power Systems is a dual-channel, high-PSRR (60dB at 100Hz) linear regulator with integrated reset circuitry, delivering up to 500mA per channel at ±1.5% output voltage accuracy (0.9V–3.3V range). It features programmable reset delay via external capacitor, 15µVRMS low-noise outputs, and operates from 2.5V–5.5V input across –40°C to +125°C. Used in portable GPS and wireless devices for stable dual-rail power with system-level reset coordination.

For engineers reviewing the MP6402DN-LF-P datasheet, MP6402DN-LF-P pinout, MP6402DN-LF-P application, or MP6402DN-LF-P equivalent, key selection criteria include dual LDO channel independence, reset monitoring of OUT2 only, SOIC8E package thermal performance (θJA = 55°C/W), and EN-active-high control logic with built-in discharge path.

Technical Context

The MP6402 employs P-channel MOSFET pass elements for both LDO channels, enabling low dropout (260mV at 500mA) and high PSRR without requiring external compensation. Its reset function is strictly tied to OUT2 voltage threshold (92.5% × VOUT2, ±3% accuracy) and uses an external capacitor on ExtCap to set delay (1.4–2.8ms typical with 3300pF).

Thermal shutdown activates at TJ = 150°C (re-engages at 130°C), and independent current limiting ensures each channel sustains ≤500mA load. The EN pin controls both regulators simultaneously; floating EN is prohibited, and internal 100Ω discharge path actively bleeds OUT1/OUT2 capacitors during disable.

Key Specifications

Pinout & Package

MP6402DN-LF-P is housed in an SOIC8E package with exposed thermal pad, supporting 2.2W continuous power dissipation at TA = +25°C and θJA = 55°C/W. Pin 1 is marked by notch or bevel; the exposed pad must be soldered to a PCB ground plane for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-LDO-with-reset applications.

Compared with XC6220B182MR-G and RP512K251D-TR-F, MP6402DN-LF-P uniquely combines 500mA dual-channel capability, ±1.5% voltage accuracy, programmable reset delay, and SOIC8E thermal performance - making it the only option for high-current, precision, and configurable reset applications.

Availability

MP6402DN-LF-P is available at Aetrix Electronics and suitable for portable GPS receivers, wireless communication modules, and Blu-ray disc players requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for MP6402DN-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan.

The MP6402 belongs to MPS's high-PSRR dual-LDO product line, engineered specifically for space-constrained consumer and portable electronics where simultaneous clean power delivery and deterministic system reset are critical.

FAQ

What is the minimum input voltage required for MP6402DN-LF-P to regulate 3.3V on OUT2?

The absolute minimum input voltage is VOUT2 + dropout voltage = 3.3V + 0.26V = 3.56V. However, the datasheet specifies guaranteed operation down to 2.5V input - meaning 3.3V output is only supported when VOUT2 is set to ≤2.8V using factory-configured options (code G). For 3.3V output, VIN must be ≥3.56V and within the 2.5V–5.5V absolute max rating.

Can MP6402DN-LF-P monitor OUT1 for reset instead of OUT2?

No. The internal reset comparator exclusively monitors the OUT2 pin voltage. The block diagram and timing diagrams confirm that RESET assertion is triggered solely by VOUT2 falling below its threshold (92.5% × VOUT2). OUT1 has no reset monitoring function - attempting to repurpose it violates the device architecture.

Is the RESET pin push-pull or open-drain, and what pull-up value is recommended?

RESET is an open-drain output requiring an external pull-up resistor to a valid logic supply (e.g., VOUT2 or system VCC). The datasheet specifies R1 > 10kΩ; a 47kΩ resistor is commonly used to balance rise time (<1µs) and leakage current (<0.1mA). Do not drive RESET directly with another IC's output - it must be pulled up.

How does the EN pin behave during power-up, and is an external pull-up required?

EN has no internal pull-up; it must be actively driven high (≥1.5V) or tied directly to IN to enable regulation. Leaving EN floating causes undefined behavior and potential latch-up. During power-up, EN should reach VIH before IN stabilizes - a simple RC delay from IN to EN ensures controlled start-up sequence without external logic.

What is the maximum allowable external capacitor on the ExtCap pin, and how does leakage affect timing?

The datasheet does not specify a hard maximum, but practical limits arise from leakage current: ceramic capacitors with <1nA leakage (e.g., X7R, C0G) are mandatory. Leakage >5nA introduces >10% error in delay time. For 2.1ms nominal delay (3300pF), use capacitors rated ≥50V to avoid voltage coefficient drift; values above 10nF increase delay nonlinearly and risk instability due to stray capacitance coupling.

Does MP6402DN-LF-P support reverse current blocking between OUT1 and OUT2?

No. The device contains no reverse-current protection diodes or MOSFET body-diode isolation between outputs. If OUT2 is powered while OUT1 is off, current can back-feed through the internal pass transistor. To prevent this, external Schottky diodes must be placed in series with each output - especially critical in systems with multiple independent power domains.

What is the thermal resistance (θJC) of the SOIC8E package, and how should the exposed pad be connected?

The SOIC8E package has θJC = 12°C/W (junction-to-case, measured at the exposed pad). The pad must be soldered to a solid copper ground plane covering ≥25mm², with ≥4 thermal vias (0.3mm diameter) connecting to inner ground layers. Failure to properly connect the pad raises θJA by >20°C/W and risks thermal shutdown at <300mA load.