Monolithic Power Systems Inc. MP6402DQT-EF-LF-P

Overview

MP6402DQT-EF-LF-P from Monolithic Power Systems is a dual-channel, high-PSRR linear regulator with integrated reset circuitry, delivering 500mA per channel at ±1.5% output voltage accuracy (0.9V–3.3V), 60dB PSRR at 100Hz, and programmable reset delay via external capacitor. It operates from 2.5V–5.5V input, features built-in short-circuit and thermal protection, and targets power-rail sequencing in portable GPS and wireless devices.

For engineers reviewing the MP6402DQT-EF-LF-P datasheet, MP6402DQT-EF-LF-P pinout, MP6402DQT-EF-LF-P application, or MP6402DQT-EF-LF-P equivalent, key selection criteria include dual LDO output voltage pairing, reset threshold accuracy (±3%), ExtCap-programmable delay timing, low-noise operation (15µVRMS), and TQFN8 thermal performance (θJA = 48°C/W).

Technical Context

The MP6402 integrates two independent P-channel MOSFET-based LDOs with separate current-limit and thermal-shutdown circuits. Each channel delivers up to 500mA with dropout voltage ≤260mV at full load and load regulation ≤50mV across 1mA–500mA.

Its reset function monitors only OUT2 voltage, asserting active-low open-drain RESET when VOUT2 falls below 92.5% of nominal, with hysteresis of 2% and delay time set by an external capacitor on ExtCap (e.g., 2.1ms with 3300pF). EN enables/disables both regulators simultaneously with logic-level control.

Key Specifications

Pinout & Package

MP6402DQT-EF-LF-P uses a 3×3mm TQFN8 package with exposed thermal pad (pin 4 = GND), optimized for PCB heat dissipation (θJA = 48°C/W on 4-layer board). Pin numbering follows standard JEDEC top-view orientation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-LDO-with-reset applications.

Compared with TPS7A2025PDBVR and MAX1725EEE+, MP6402DQT-EF-LF-P uniquely combines dual 500mA LDOs, ±1.5% accuracy, programmable reset delay, and 60dB PSRR-enabling compact, noise-immune, self-monitoring power solutions unattainable with single-channel alternatives.

Availability

MP6402DQT-EF-LF-P is available at Aetrix Electronics and suitable for portable GPS receivers, wireless communication modules, Blu-ray player logic boards, and consumer audio DSP systems requiring stable component supply across automotive and industrial temperature ranges.

Supply support for MP6402DQT-EF-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan.

The MP6402 belongs to MPS's dual-LDO-with-integrated-reset product line, engineered for space-constrained, battery-powered applications demanding coordinated power sequencing, low noise, and autonomous fault response.

FAQ

What is the minimum recommended input voltage for MP6402DQT-EF-LF-P?

The absolute minimum input voltage is 2.5V per datasheet specifications. Operation below this level risks dropout and loss of regulation on either channel. For reliable 2.5V output, VIN must be ≥2.76V (2.5V + 260mV dropout); for 3.3V output, VIN must be ≥3.56V.

Can OUT1 and OUT2 be configured to the same voltage?

Yes-Table 1 lists code "E" (1.8V/1.8V), "F" (2.5V/2.5V), and "G" (2.8V/2.8V) as valid factory-configured options. However, the datasheet explicitly recommends OUT2 ≥ OUT1 to ensure proper reset functionality and avoid unintended assertion during startup.

How does the ExtCap pin affect reset timing accuracy?

ExtCap sets reset delay via RC charging; timing error scales with capacitor tolerance and PCB stray capacitance. Using a 1% C0G/NP0 ceramic capacitor minimizes drift. The formula T_D = 0.6 × C₄(nF) + 0.1ms assumes ideal conditions-layout parasitics may add ±10% uncertainty.

Is the RESET pin compatible with 1.8V logic systems?

Yes-RESET is open-drain with V_OL ≤0.2V at 2mA sink current, ensuring solid low-state margin even with 1.8V supply rails. An external pull-up to the target logic domain (e.g., 1.8V or 3.3V) is required per application circuit guidelines.

Does MP6402DQT-EF-LF-P support reverse current blocking?

No-the device uses P-MOSFET pass elements without intrinsic body-diode reverse-blocking capability. If reverse current flow from OUT to IN is possible (e.g., during hot-swap), an external Schottky diode or ideal diode controller is required on the input rail.

What is the thermal pad connection requirement for TQFN8 package?

The exposed thermal pad (pin 4) must be soldered to a dedicated PCB copper pour tied to GND. Minimum recommended land pattern is 2.5mm × 2.5mm with 4–6 thermal vias (0.3mm diameter) to inner ground planes-failure to do so degrades θJA by >15°C/W and risks thermal shutdown.

Can EN be driven by a microcontroller GPIO without level shifting?

Yes-EN threshold is V_IH = 1.5V (min) and V_IL = 0.6V (max), making it compatible with 1.8V, 3.3V, and 5V logic families. No level shifter is needed; however, the pin must never be left floating due to risk of erratic enable behavior.