Monolithic Power Systems Inc. MP6534GU-P

Overview

MP6534GU-P from Monolithic Power Systems is a three-phase brushless DC motor pre-driver IC with integrated 500mA buck regulator and regulated charge pump gate drive supply. It drives six external N-channel MOSFETs in half-bridge configuration across 5V–55V input, supports 100% duty cycle via trickle-charge bootstrap, and delivers 0.8A source / 1A sink gate drive current. Used in e-bike motor controllers where compact high-voltage gate driving and local MCU power generation are required.

For engineers reviewing the MP6534GU-P datasheet, MP6534GU-P pinout, MP6534GU-P application, or MP6534GU-P equivalent, key selection considerations include its 5–55V wide VIN range, programmable dead-time control (30ns–6µs), VDS-based short-circuit protection with 0.8–2.62V OCREF threshold, integrated buck regulator with 0.812V feedback reference, and thermal shutdown at 150°C.

Technical Context

The MP6534GU-P implements a three-phase gate driver architecture with independent ENx/PWMx logic per phase, using a regulated charge pump to generate ~11.5V VREG for low-side drive and bootstrap + trickle-charge circuitry for high-side drive. Its VDS-sensing short-circuit protection compares MOSFET drain-source voltage against an externally set OCREF reference, while over-current protection monitors LSS shunt voltage with 0.4–0.6V threshold.

The integrated buck regulator operates in current-mode control with 330–570kHz switching frequency, 1.0–1.5A current limit, and foldback protection triggered below 250mV FB voltage. It features REN enable with 1.35V rising threshold, 0.792–0.832V feedback reference, and thermal shutdown at 165°C with 20°C hysteresis.

Key Specifications

Pinout & Package

The MP6534GU-P is housed in a thermally enhanced 40-pin QFN package (5mm × 5mm) with exposed thermal pad for efficient heat dissipation in motor drive applications.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar three-phase BLDC pre-driver applications.

Compared with MP6532GU-Z, the MP6534GU-P adds critical 500mA buck regulation and extends VIN to 55V-enabling direct use with 48V e-bike batteries and eliminating external regulators. Versus TB9054FG, it trades SPI configurability for higher gate drive strength, wider voltage range, and hardware-based VDS fault detection essential for rugged motor environments.

Availability

MP6534GU-P is available at Aetrix Electronics and suitable for e-bike motor controllers, power drill inverters, industrial fan drivers, and automotive HVAC blowers requiring stable component supply across automotive, industrial, and consumer production programs.

Supply support for MP6534GU-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with core expertise in DC/DC conversion, motor control, and gate driver technology.

The MP6534 product line targets high-voltage, high-reliability BLDC motor control applications-designed to integrate gate driving, protection, and local power generation in a single compact package for battery-powered and industrial motion systems.

FAQ

What is the maximum allowable input voltage for MP6534GU-P?

The absolute maximum VIN rating is 65V, but the recommended operating range is 5V to 55V. Exceeding 55V may trigger UVLO or cause reliability issues; transient spikes above 65V-even briefly-risk permanent damage. For 48V battery systems, TVS clamping at VIN is recommended to suppress load-dump events.

How does the trickle-charge circuit enable 100% duty cycle operation?

The internal trickle-charge circuit supplies ~5µA to each bootstrap capacitor during high-side conduction, compensating for leakage and maintaining sufficient gate voltage even when the low-side MOSFET never turns on. This eliminates the need for external charge pumps or complex bootstrap diode networks in continuous conduction mode.

Can MP6534GU-P drive both N-channel and P-channel high-side MOSFETs?

No-it is designed exclusively for N-channel high-side MOSFETs using bootstrap or charge-pump gate drive. The architecture assumes low-side N-MOSFETs and requires external high-side N-MOSFETs with appropriate gate threshold and R_DS(on). P-channel high-side configurations are not supported due to lack of dedicated high-voltage level-shifting for PMOS gate control.

What is the purpose of the OCREF and LSS pins, and how do they differ in fault detection?

OCREF sets the VDS threshold for short-circuit detection across all six MOSFETs, triggering immediate latch-off if any drain-source voltage exceeds the reference. LSS monitors low-side shunt voltage for over-current protection, with a fixed 0.4–0.6V threshold. OCREF detects MOSFET failure or wiring shorts; LSS detects excessive motor phase current-providing complementary, hardware-based fault coverage.

Is the buck regulator synchronous or asynchronous, and what is its switching frequency?

The buck regulator is asynchronous, using an internal N-channel MOSFET switch and requiring an external Schottky diode. Its nominal switching frequency is 450kHz (range 330–570kHz), with foldback reducing frequency to 135kHz during output short-circuit to limit peak current and thermal stress.

How is thermal performance managed in the QFN-40 package?

The QFN-40 (5mm × 5mm) package features an exposed thermal pad soldered to a large PCB copper area. With a θ_JA of 36°C/W on a 4-layer board, it dissipates up to 3.47W continuously at 25°C ambient. Thermal shutdown activates at 150°C junction temperature, and the latched fault state prevents self-heating until reset via nSLEEP or VIN UVLO recovery.

Does MP6534GU-P support sensorless BLDC commutation?

Yes-the IC provides the gate drive infrastructure (PWM inputs, ENx enables, dead-time control, fault signaling) required for sensorless algorithms. However, it does not include integrated back-EMF sensing or commutation logic; those functions must be implemented externally in the MCU or FPGA controlling PWMA/PWMB/PWMC timing.