Monolithic Power Systems Inc. MP6900DS-LF-Z

Overview

MP6900DS-LF-Z from Monolithic Power Systems is a fast turn-off intelligent synchronous rectifier controller for flyback converters, replacing Schottky diodes with external MOSFETs. It regulates forward voltage drop to 70mV, achieves 20ns total turn-off delay, supports up to 400kHz switching, operates from 8V–24V VDD, and delivers <3mA quiescent current in SOIC-8 package.

For engineers reviewing the MP6900DS-LF-Z datasheet, MP6900DS-LF-Z pinout, MP6900DS-LF-Z application, or MP6900DS-LF-Z equivalent, key selection criteria include VD sensing range (−0.7V to +180V), gate drive capability (2A pull-down), thermal shutdown (170°C), and compatibility with CCM/DCM/QR topologies in notebook adapters and industrial power supplies.

Technical Context

The MP6900DS-LF-Z implements adaptive gate control using VD–VSS differential sensing to regulate MOSFET conduction at ~70mV forward drop and trigger turn-off when VD–VSS exceeds 30mV. Its blanking circuit enforces 200ns minimum on-time and dynamically adjusts turn-off threshold to +50mV during turn-on to prevent false triggering.

It integrates a high-voltage JFET input stage for VD clamping up to 180V, internal 10kΩ pull-down on VG, and UVLO with 6.0V rising threshold and 1.2V hysteresis. Thermal shutdown activates at 170°C with 50°C hysteresis, and enable functionality is implemented only on SOIC-8 via EN pin (0.8V low, 2V high).

Key Specifications

Pinout & Package

MP6900DS-LF-Z uses SOIC-8 package with exposed thermal pad (θ_JA = 90°C/W, θ_JC = 45°C/W). Pin functions are validated per datasheet Rev. 1.14, with EN pin active only in this variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous rectifier controller applications.

Compared with NCP4306DR2G and discrete MOSFET solutions, MP6900DS-LF-Z uniquely combines CCM/DCM/QR support, SOIC-8 thermal performance (1.39W), and sub-25ns turn-off in a single IC-enabling higher power density and lower system-level BOM cost in certified AC/DC adapters.

Availability

MP6900DS-LF-Z is available at Aetrix Electronics and suitable for industrial power systems, distributed power architectures, and flyback converter designs requiring stable component supply, RoHS-compliant packaging, and long-term lifecycle assurance.

Supply support for MP6900DS-LF-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, headquartered in Kirkland, WA, with global design and support centers.

The MP6900 product line targets high-efficiency secondary-side synchronous rectification in AC/DC flyback converters, emphasizing fast turn-off, wide V_D range, and topology-agnostic operation for consumer, industrial, and computing power supplies.

FAQ

What is the function of the EN pin on MP6900DS-LF-Z?

The EN pin is an active-high enable input exclusive to the SOIC-8 package. When pulled below 0.8V, it places the device in sleep mode with 250µA shutdown current. At ≥2V, normal operation resumes. This pin is not present in TSOT23-5 or QFN6 variants and must be tied high or controlled via system microcontroller for standby sequencing.

Can MP6900DS-LF-Z drive both high-side and low-side synchronous rectifiers?

Yes-MP6900DS-LF-Z supports both configurations. In high-side mode, VSS connects to secondary ground and VD senses MOSFET drain; in low-side mode, VSS connects to secondary output and VD senses source node. The datasheet confirms compatibility with either topology via proper PCB routing and grounding separation between PGND and VSS.

What MOSFET R_DS(on) is recommended for use with MP6900DS-LF-Z?

Per MPS application guidance, R_DS(on) should be ≥35/I_OUT (mΩ) - e.g., ≥7mΩ for 5A output. Lower R_DS(on) causes excessive gate drive saturation and diminishes the 70mV regulation benefit. MOSFETs with Q_g ≤120nC ensure full gate turn-on within 300ns, minimizing body-diode conduction loss.

How does the blanking function affect minimum on-time in CCM operation?

The MP6900DS-LF-Z enforces a 200ns minimum on-time via blanking logic. During this period, the turn-off threshold shifts from −30mV to +50mV to suppress false triggering from gate ringing. Setting synchronous periods below 200ns in CCM risks shoot-through; thus, minimum practical switching period is 200ns (5MHz), though max rated frequency remains 400kHz.

Is thermal derating required for continuous operation at 400kHz?

Yes-above 100kHz, with VDD >15V or C_LOAD >5nF, power dissipation exceeds 100mW. The SOIC-8 package's 1.39W rating at 25°C ambient requires thermal pads and ≥2 oz copper on inner layers. At 400kHz and 24V VDD, junction temperature must be verified using θ_JA = 90°C/W; exceeding 125°C TJ requires heatsinking or frequency reduction.

Does MP6900DS-LF-Z require external components for VD clamping?

A small resistor (typically 10–100Ω) is recommended between VD and the MOSFET drain to limit current if V_D falls below −0.7V, protecting the internal HV JFET. No TVS or Zener is needed-the datasheet specifies the JFET handles up to 180V, and the resistor prevents latch-up during negative transients from transformer leakage.

What is the significance of separate PGND and VSS pins?

PGND carries high di/dt gate sink current and must connect to power ground plane; VSS is the precision reference for VD sensing and comparator thresholds. Separating them prevents noise coupling into the 30mV turn-off threshold detection, ensuring reliable zero-crossing detection across load and line variations.