Monolithic Power Systems Inc. MP6902DS-LF

Overview

MP6902DS-LF from Monolithic Power Systems is a fast turn-off intelligent synchronous rectifier controller for flyback converters, replacing Schottky diodes with an external MOSFET to achieve high efficiency. It regulates V_DS to ~70 mV in forward conduction, shuts off within 20 ns of negative V_DS detection, supports DCM and quasi-resonant operation, and enters light-load sleep mode drawing <300 µA. Used in notebook adapters and industrial flyback power supplies.

For engineers reviewing the MP6902DS-LF datasheet, MP6902DS-LF pinout, MP6902DS-LF application, or MP6902DS-LF equivalent, key selection criteria include V_DS regulation accuracy (±15 mV), total turn-off delay (≤45 ns at 10 nF load), SOIC8 package compatibility, light-load timing programmability via R_LL, and support for both high-side and low-side rectification topologies.

Technical Context

The MP6902DS-LF implements adaptive gate control using dual voltage thresholds: −70 mV for forward conduction regulation and −30 mV for fast turn-off, with blanking logic to suppress noise-induced false triggering. Its internal UVLO (6.0 V rising, 1.0 V hysteresis) and thermal shutdown (150 °C trip, 30 °C hysteresis) ensure robust operation across 8–24 V V_DD.

It features programmable light-load latch-off via external resistor on LL pin (30–300 kΩ), enabling entry into <300 µA quiescent current mode when conduction time falls below T_LL + 100 µs delay. Gate drive output delivers 13–15 V high-level swing (V_DD > 17 V) and pulls down with ≤2 Ω impedance for rapid MOSFET turn-off.

Key Specifications

Pinout & Package

MP6902DS-LF is housed in an industry-standard SOIC8 package (JEDEC MS-012 AA), with exposed pad optional per variant - this variant uses standard SOIC8 without thermal pad. Pin functions are validated per Monolithic Power Systems Rev. 1.14 datasheet (June 2014).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous rectifier controller applications.

Compared with NCP4306DR2G and SiHP20N60E, MP6902DS-LF offers programmable light-load timing, tighter 70 mV regulation tolerance (±15 mV), and faster 35 ns turn-off delay-critical for high-frequency QR flyback designs where MOSFET body diode conduction loss dominates efficiency at light loads.

Availability

MP6902DS-LF is available at Aetrix Electronics and suitable for USB-C power adapters, industrial flyback PSUs, battery charger auxiliary supplies, and distributed telecom power modules requiring stable component supply and long-term lifecycle support.

Supply support for MP6902DS-LF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, headquartered in Kirkland, WA, with global design and support centers.

The MP6902 belongs to MPS's intelligent synchronous rectifier controller product line, engineered specifically for high-efficiency flyback converters targeting energy-efficient AC-DC adapters, industrial power supplies, and telecom infrastructure where Schottky diode replacement delivers measurable thermal and efficiency gains.

FAQ

What is the maximum recommended V_DS spike the MP6902DS-LF can withstand on the VD pin?

The VD pin is rated for absolute maximum 180 V. For reliable operation, the sum of output voltage, reflected input voltage (V_IN/n), and drain spike must remain below 180 V × 0.7–0.8 de-rating factor. Example: In a 24 V output, 400 V input, n = 10 flyback, max allowable V_DS spike is ~180 V − (24 V + 40 V) = 116 V.

Can MP6902DS-LF drive both high-side and low-side MOSFET configurations?

Yes - it supports both topologies. For high-side use, VSS connects to MOSFET source and VD senses drain; for low-side, VSS connects to system ground and VD senses source. The datasheet provides dedicated auxiliary winding schematics for each case (Figures 9–10).

How does the light-load timing resistor (R_LL) affect startup behavior?

R_LL sets only the light-load enter delay (T_LL ≈ 2.2 µs × R_LL), not startup. Startup is governed by VDD UVLO (6.0 V rising). Once enabled, MP6902DS-LF begins normal regulation immediately; R_LL only determines how long low conduction must persist before entering <300 µA sleep mode.

What is the minimum external MOSFET R_DS(on) recommended for optimal efficiency?

MPS recommends R_DS(on) ≥ 35 mΩ / I_OUT (e.g., ≥7 mΩ for 5 A output). Too-low R_DS(on) causes excessive gate drive reduction during regulation, diminishing efficiency gains. This balances conduction loss against gate drive overhead and body diode conduction time.

Does MP6902DS-LF require a minimum load to maintain regulation stability?

No minimum load is required. Regulation remains active down to zero load - the controller continues adjusting VG to hold V_DS near −70 mV until light-load conditions persist long enough to trigger latch-off (programmed by R_LL). No external bias or dummy load is needed.

Is the NC pin (Pin 7) electrically isolated or internally tied?

Pin 7 is a true no-connect: not bonded to die, not internally tied to any node. It must remain unconnected on PCB layout. Routing traces or placing copper near Pin 7 has no electrical effect but may impact thermal performance if adjacent to heat-generating components.