Monolithic Power Systems Inc. MP6905GS

Overview

MP6905GS from Monolithic Power Systems is a fast-turn-off intelligent rectifier controller IC designed to replace Schottky diodes in high-efficiency flyback converters. It regulates external MOSFET conduction to maintain ~30mV forward drop, achieves 20ns total turn-off delay, supports CCM/DCM/QR topologies, and operates with 8–24V VDD supply-enabling up to 1.5W power savings in notebook adapters.

For engineers reviewing the MP6905GS datasheet, MP6905GS pinout, MP6905GS application, or MP6905GS equivalent, key selection considerations include its light-load sleep mode (<300µA quiescent current), dual-side rectification support (high-side/low-side), gate drive capability for 12V/5V logic-level FETs, and thermal shutdown protection at 150°C junction temperature.

Technical Context

The MP6905GS implements adaptive synchronous rectification using voltage-sense-based control of an external MOSFET's gate. Its core operation relies on real-time monitoring of V_DS across the external switch via the VD–VSS differential input, triggering turn-on when V_DS < –30mV and turn-off when V_DS > 0mV, with 20ns total propagation delay and blanking intervals to suppress noise-induced false triggering.

It integrates a programmable light-load latch-off function (set by external resistor on LL pin), under-voltage lockout (6.0V rising threshold), enable-controlled shutdown (<500µA), and internal thermal shutdown (150°C trip, 120°C hysteresis), all within a SOIC-8 package optimized for secondary-side placement in isolated flyback systems.

Key Specifications

Pinout & Package

MP6905GS is housed in a standard SOIC-8 package (JEDEC MS-012, variation AA) with exposed pad not electrically connected. Pin 1 is marked by a notch or dot; pins are numbered counterclockwise from top-left in top view.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar intelligent rectifier controller applications.

Compared with MP6906GS and SRK1001, MP6905GS delivers balanced performance for mid-frequency flyback designs with dual-side flexibility and proven field reliability, while MP6906GS improves timing precision and SRK1001 trades versatility for integration in constrained high-side layouts.

Availability

MP6905GS is available at Aetrix Electronics and suitable for USB-C PD adapters, industrial flyback SMPS, medical equipment power supplies, and LED driver secondary-side rectification requiring stable component supply and long-lifecycle support.

Supply support for MP6905GS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP6905GS belongs to MPS's intelligent rectifier controller product line, engineered specifically to replace Schottky diodes in isolated flyback converters-prioritizing efficiency, thermal robustness, and ease of layout in space-constrained secondary-side applications.

FAQ

What is the recommended external MOSFET R_DS(ON) range for MP6905GS?

The MP6905GS regulates V_DS to ~30mV during conduction, so conduction loss becomes I_OUT × 30mV regardless of R_DS(ON). However, excessively low R_DS(ON) (e.g., <3mΩ at 5A) causes premature turn-off due to V_DS crossing the –30mV threshold too quickly. For 5A output, R_DS(ON) ≥3mΩ is advised; consult Figure 5 in the datasheet for load-dependent guidance.

Can MP6905GS be used in high-side rectification with transformer center-tap configuration?

Yes-MP6905GS supports high-side rectification, including center-tapped secondaries. The VD–VSS sensing loop must connect directly to the MOSFET drain and source, and VDD must be supplied via an auxiliary winding or LDO since the output voltage is not referenced to earth ground. Layout guidelines in Section 13 emphasize minimizing the VD/VSS loop area to prevent noise coupling.

How does the light-load latch-off function improve efficiency?

The light-load latch-off disables gate switching when conduction time falls below a user-defined threshold (set by LL resistor), eliminating gate charge/discharge losses and driver quiescent current. This reduces total system no-load power to <300µA-critical for meeting Energy Star 1W standby limits-while maintaining fast wake-up response when load increases.

Is MP6905GS pin-compatible with MP6904 or MP6908?

No-MP6905GS has unique pin assignments: PGND (Pin 1), EN (Pin 2), LL (Pin 3), VD (Pin 4), VSS (Pin 5), VDD (Pin 6), NC (Pin 7), VG (Pin 8). MP6904 uses different pinout (e.g., VDD on Pin 8), and MP6908 integrates additional features like VDD OVP and requires different biasing. Direct substitution is not possible without PCB redesign.

What layout practices prevent false triggering on the VD pin?

To prevent false triggering, route VD and VSS as a tightly coupled, short-length differential pair directly to the MOSFET drain and source pads-avoiding shared traces with power loops or gate drivers. Place a 100nF ceramic capacitor between VD and VSS near the IC, and keep the VD trace away from noisy nodes like VG or transformer windings. Follow Figure 11's sensing loop isolation recommendation strictly.

Does MP6905GS require external bootstrap components for gate drive?

No-MP6905GS integrates a self-contained gate driver with push-pull output and active pull-down (~1Ω impedance), eliminating need for external bootstrap diodes or capacitors. It derives gate drive energy directly from VDD, making it suitable for both high-side and low-side configurations without auxiliary charge pumps or floating supplies.

What is the maximum allowable V_DS slew rate during turn-off to avoid false triggering?

The MP6905GS includes 200ns blanking after turn-on and turn-off to suppress dV/dt-induced false triggers. While no explicit slew-rate limit is specified, layout best practices (small VD/VSS loop, proper decoupling, separation from power paths) ensure reliable operation even with dV/dt exceeding 50V/ns-verified in typical 90W QR flyback waveforms shown in Figures 8 and 14.