Monolithic Power Systems Inc. MP6906GJ-Z

Overview

MP6906GJ-Z from Monolithic Power Systems is a fast turn-off intelligent rectifier IC designed to replace Schottky diodes in high-efficiency flyback converters. It regulates external MOSFET V_DS to ~30mV during conduction, achieves 25ns total turn-off delay, supports both high-side and low-side synchronous rectification, and operates across 4.2V–35V V_DD. It enables power savings up to 1.5W in notebook adapters.

For engineers reviewing the MP6906GJ-Z datasheet, MP6906GJ-Z pinout, MP6906GJ-Z application, or MP6906GJ-Z equivalent, this page delivers verified technical context, package-specific pin mapping, real-world efficiency trade-offs, light-load timing design guidance, and validated alternative options for synchronous rectifier selection in DCM/QR/CCM flyback topologies.

Technical Context

The MP6906GJ-Z implements adaptive V_DS-sensing control with programmable turn-on blanking (~1.6µs) and turn-off blanking (triggered at V_DS ≥ 2V), enabling precise regulation of forward voltage to 30mV while suppressing false triggering during ringing. Its rail-to-rail gate driver delivers 10.5–13V high-side drive and 50mV low-side pull-down under load.

It integrates dual-mode operation: automatic DCM/QR detection via V_DS polarity sensing and CCM support via SYNC input (2V threshold, 40–70ns propagation delay). Light-load entry is controlled by external R_LL (T_LL = 6.3×R_LL/200kΩ µs), reducing quiescent current to 150µA while maintaining latch-off behavior until body-diode conduction exceeds T_LL + 0.6µs.

Key Specifications

Pinout & Package

MP6906GJ-Z uses the TSOT23-6 package: 2.9mm × 1.6mm × 0.85mm, 6-pin surface-mount, exposed pad optional (not electrically connected per datasheet).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous rectifier controller applications.

Compared with MP6906GJ-Z, NCP4306DR2G offers lower unit cost but forfeits programmable light-load timing and CCM control, while the Vishay discrete pair increases design complexity and footprint without delivering the 30mV regulation precision or 25ns turn-off speed.

Availability

MP6906GJ-Z is available at Aetrix Electronics and suitable for USB-C PD adapters, industrial flyback PSUs, medical equipment power modules, and telecom DC-DC brick converters requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant sourcing.

Supply support for MP6906GJ-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with over 20 years of leadership in DC/DC conversion, motor drivers, and power management.

The MP6906 product line targets high-efficiency AC/DC and isolated DC/DC converters, specifically engineered to replace Schottky diodes in flyback topologies while delivering precise V_DS regulation, ultra-fast turn-off, and multi-mode operational flexibility.

FAQ

What is the maximum drain voltage the MP6906GJ-Z can sense on the VD pin?

The MP6906GJ-Z VD pin supports up to +180V relative to VSS, enabled by an integrated high-voltage JFET front-end. This allows direct connection to MOSFET drains in 100W+ flyback designs without external voltage clamping, provided the recommended 1kΩ resistor is placed between VD and the MOSFET drain to limit current during negative V_G transients.

How does the light-load mode timing work, and what resistor value sets a 3.5µs TLL?

TLL is calculated as TLL = 6.3 × R_LL / 200kΩ (µs). For 3.5µs, R_LL = (3.5 × 200kΩ) / 6.3 ≈ 111kΩ. The IC monitors the MOSFET conduction period; if it remains below TLL for longer than the light-load-enter delay (75–115µs), gate drive latches off, reducing quiescent current to 150µA until body-diode conduction exceeds TLL + 0.6µs.

Can the MP6906GJ-Z be used in high-side rectification without an auxiliary winding?

Yes - the MP6906GJ-Z supports high-side rectification using power derived from the secondary winding via a diode (Figure 13), provided the winding voltage stays ≤35V. If voltage exceeds 35V, an external Zener-based LDO (Figure 15) is required. Its 4.2V–35V V_DD range eliminates auxiliary winding in many 12V–24V output systems.

What is the purpose of separating PGND and VSS, and how should they be routed?

PGND carries gate drive return current; VSS is the precision reference for V_D sensing. Separating them prevents switching noise from corrupting V_DS measurement. Route VSS directly to the MOSFET source with a short, low-inductance path; keep PGND loop small and physically isolated from VSS traces; use separate copper pours or split planes with single-point connection at the IC.

Does the MP6906GJ-Z require external components for basic operation, and which are mandatory?

Four components are mandatory: (1) ≥1µF ceramic capacitor from VDD to PGND; (2) resistor on LL to set light-load timing (or leave open for no light-load mode); (3) 1kΩ resistor between VD and MOSFET drain for overvoltage protection; (4) gate resistor (R_GATE) selected per MOSFET Q_g to balance switching speed and EMI. No external bootstrap or timing capacitors are needed.

How does the SYNC pin enable reliable CCM operation, and what signal levels are acceptable?

The SYNC pin accepts a logic-high signal (>2V) to immediately disable the gate driver, forcing CCM by preventing MOSFET turn-on during reverse current flow. It tolerates 0–6.5V input, with internal 10–15µA pull-down. A microcontroller GPIO or PWM controller output can drive it directly; no level-shifting is required for 3.3V or 5V systems.

What MOSFET R_DS(ON) is recommended for a 5A output application, and why?

For 5A output, R_DS(ON) ≥ 3mΩ is recommended. Since conduction loss is fixed at ≈ I_SD × 30mV, lower R_DS(ON) increases gate charge (Q_g) and slows switching, raising driver loss. Also, V_DS = –I_SD × R_DS(ON); if R_DS(ON) is too low, V_DS drops below –50mV, causing premature turn-off before full conduction is achieved.